DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 and 21-25 in the reply filed on 02/11/2026 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/11/2026.
Claim Objections
Claims 1-15 and 21-25 are objected to because of the following informalities:
Claim 1 (claims 8 and 21) recites “2-D material” (line 3) which should be replaced with “two-dimensional (2-D) material”.
Claim 8 recites “2-D material” (line 3) which should be replaced with “two-dimensional (2-D) material”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0345944 to Lin et al. (hereinafter Lin).
With respect to claim 1, Lin discloses a method (e.g., forming a hetero-structure field-effect transistor, see the annotated Figs. 2A and 12A below) (Lin, Figs. 1A-4A, 9A, 10, 12A, ¶0014, ¶0016-¶0050), comprising:
forming a gate electrode (212) (Lin, Fig. 12A, ¶0049) in contact with a gate dielectric layer (104) (Lin, Fig. 12A, ¶0017, ¶0049);
forming a first 2-D material buffer layer (106) (Lin, Figs. 2A, 12A, ¶0019-¶0022, ¶0049) over the gate dielectric layer (104);
forming a 2-D material channel layer (108) (Lin, Figs. 2A, 12A, ¶0019-¶0020, ¶0023, ¶0049) over the first 2-D material buffer layer (106); and
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forming source/drain electrodes (112/114) (Lin, Figs. 3A, 12A, ¶0026-¶0027, ¶0049) over source/drain regions of the 2-D material channel layer (108).
Regarding claim 2, Lin discloses the method of claim 1. Further, Lin discloses the method, further comprising forming a second 2-D material buffer layer (e.g., the hetero-structure stack 110 including a second buffer layer 182/192, as in Fig. 9A or Fig. 10) (Lin, Figs. 9A, 10, 12A, ¶0046-¶0047, ¶0049) over the 2-D material channel layer (108).
Regarding claim 3, Lin discloses the method of claim 2. Further, Lin discloses the method, wherein the first and second 2-D material buffer layers (106 and 182/192) (Lin, Figs. 9A, 10, 12A, ¶0020, ¶0046-¶0047, ¶0049) are made of a different 2-D material (e.g., WS2) (Lin, Figs. 9A, 10, 12A, ¶0046-¶0047) than the 2-D material channel layer (108, MoS2) (Lin, Figs. 9A, 10, 12A, ¶0020).
Regarding claim 4, Lin discloses the method of claim 2. Further, Lin discloses the method, wherein, wherein the 2-D material channel layer (108) is in contact with the source/drain electrodes (112/114) (Lin, Figs. 3A, 9A, 10, 12A, ¶0026-¶0027, ¶0046-¶0047, ¶0049).
With respect to claim 21, Lin discloses a method (e.g., forming a hetero-structure field-effect transistor, see the annotated Fig. 12A above) (Lin, Figs. 1A, 2A, 3A, 9A, 10, 12A, ¶0014, ¶0016-¶0050), comprising:
forming a gate dielectric layer (104) (Lin, Figs. 1A, 12A, ¶0016-¶0017, ¶0049) over a substrate (102);
forming a first 2-D material buffer layer (106) (Lin, Figs. 1A, 12A, ¶0019-¶0022, ¶0049) over the gate dielectric layer (104);
forming a 2-D material channel layer (108) (Lin, Figs. 1A, 12A, ¶0019-¶0020, ¶0023, ¶0049) over the first 2-D material buffer layer (106); and
forming source/drain electrodes (112/114) (Lin, Figs. 3A, 12A, ¶0026-¶0027, ¶0049) over source/drain regions of the 2-D material channel layer (108).
Regarding claim 22, Lin discloses the method of claim 21. Further, Lin discloses the method, wherein the first 2-D material buffer layer (106) (Lin, Figs. 1A, 12A, ¶0020, ¶0049) is made of a different 2-D material (e.g., WS2) (Lin, Figs. 1A, 12A, ¶0020) than the 2-D material channel layer (108, MoS2).
Regarding claim 23, Lin discloses the method of claim 21. Further, Lin discloses the method, further comprising, after forming the source/drain electrodes (Lin, Figs. 3A, 4A, 12A, ¶0028, ¶0046, ¶0049), forming a second 2-D material buffer layer (e.g., 182, the second buffer layer 182 and gate stack 120 are collectively patterned to form a stack between the source/drain electrodes 112/114 after forming the source/drain electrodes 112/114, as in Figs. 3A-4A) over the 2-D material channel layer (108).
Claims 1 and 21-22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0335587 to Tung et al. (hereinafter Tung).
With respect to claim 1, Tung discloses a method (e.g., forming field-effect bottom-gate transistor, see the annotated Fig. 10 below) (Tung, Figs. 10, 17, ¶0031, ¶0046, ¶0055-¶0058), comprising:
forming a gate electrode (1014, HfO2) (Tung, Fig. 10, ¶0046) in contact with a gate dielectric layer (1004, HfO2);
forming a first 2-D material buffer layer (e.g., 1006, hBN) (Tung, Fig. 10, ¶0046, ¶0057) over the gate dielectric layer (1004, HfO2);
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forming a 2-D material channel layer (120, MoS2) (Tung, Fig. 10, ¶0046, ¶0055-¶0057) over the first 2-D material buffer layer (e.g., 1006, hBN); and
forming source/drain electrodes (1010/1012) (Tung, Fig. 10, ¶0046, ¶0057) over source/drain regions of the 2-D material channel layer (120, MoS2).
With respect to claim 21, Tung discloses a method (e.g., forming field-effect bottom-gate transistor, see the annotated Fig. 10 above) (Tung, Figs. 10, 17, ¶0031, ¶0046, ¶0055-¶0058), comprising:
forming a gate dielectric layer (1004, HfO2) (Tung, Fig. 10, ¶0046, ¶0057) over a substrate (1002);
forming a first 2-D material buffer layer (e.g., 1006, hBN) (Tung, Fig. 10, ¶0046, ¶0057) over the gate dielectric layer (1004);
forming a 2-D material channel layer (120, MoS2) (Tung, Fig. 10, ¶0046, ¶0055-¶0057) over the first 2-D material buffer layer (1006); and
forming source/drain electrodes (1010/1012) (Tung, Fig. 10, ¶0046, ¶0057) over source/drain regions of the 2-D material channel layer (120).
Regarding claim 22, Tung discloses the method of claim 21. Further, Tung discloses the method, wherein the first 2-D material buffer layer (1006, hBN) (Tung, Fig. 10, ¶0046, ¶0057) is made of a different 2-D material (e.g., hBN) than the 2-D material channel layer (120, MoS2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Shepard et al. (US 2016/0240692, hereinafter Shepard).
Regarding claims 2 and 3, Tung discloses the method of claim 1. Further, Tung does not specifically disclose the method, further comprising forming a second 2-D material buffer layer over the 2-D material channel layer (as claimed in claim 2); wherein the first and second 2-D material buffer layers are made of a different 2-D material than the 2-D material channel layer (as claimed in claim 3).
However, Shepard teaches forming a hetero-structure (e.g., 206/202/204 or 608/602/606) (Shepard, Figs. 2, 4, 6, ¶0007-¶0014, ¶0055-¶0079, ¶0097) comprising a 2-D material layer (202 or 602) (Shepard, Figs. 2, 4, 6, ¶0057-¶0059) including graphene or MoS2 material layer encapsulated between a first buffer layer (206 or 608) and a second buffer layer (204 or 606) comprised of hexagonal boron nitride (hBN) or other 2-D material that is different from the 2-D material layer (202 or 602), to reduce environmental sensitivity, to control band structure, and to provide 2D FETs having high mobility (Shepard, ¶0048, ¶0075-¶079, ¶0097).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung by forming a hetero-structure comprising a 2-D material layer encapsulated between a first buffer layer and a second buffer layer as taught by Shepard to have the method, further comprising forming a second 2-D material buffer layer over the 2-D material channel layer (as claimed in claim 2); wherein the first and second 2-D material buffer layers are made of a different 2-D material than the 2-D material channel layer (as claimed in claim 3), in order to reduce environmental sensitivity of the channel layer, and to provide 2D FET having high mobility (Shepard, ¶0004, ¶0007-¶0014, ¶0048, ¶0057-¶0059, ¶0075-¶079, ¶0097).
Regarding claim 4, Tung in view of Shepard discloses the method of claim 2. Further, Tung discloses the method, wherein, wherein the 2-D material channel layer (120) is in contact with the source/drain electrodes (1010/1012) (Tung, Fig. 10, ¶0046, ¶0057).
Claims 5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Hong et al. (KR 20130026679 A, hereinafter Hong).
Regarding claim 5, Tung discloses the method of claim 1. Further, Tung discloses the method, wherein the 2-D material channel layer (120) is formed by: performing a first polydimethylsiloxane (PDMS) stamping process (e.g., PDMS-assisted approach using PDMS film 130, as in Fig. 1G, to transfer MoS2 channel layer 120 to a target substrate 1002 hBn/HfO2/Si including a first buffer layer hBN) (Tung, Fig. 10, ¶0046, ¶0056-¶0057) to transfer the 2-D material channel layer (120) to the first 2-D material buffer layer (1006, hBN), but does not specifically disclose performing a first annealing process to reduce a surface roughness of the 2-D material channel layer.
However, Hong teaches a method of transferring 2D material (e.g., graphene) (Hong, Figs. 3(a)-3(c), Abstract, pp. 1-9) on a SiO2/Si substrate by using polymer layer (e.g., PMMA), and performing a heat treatment at specific temperature (e.g., 500º C) after transfer of the 2D material to remove polymer residues form the surface of the 2D material, wherein after heat treatment the surface roughness (Hong, Figs. 3(a)-3(c), pp. 6-7) of the 2D material decreases due to complete removal of the polymer residues. Thus, a person of ordinary skill in the art would recognize that heat treatment at specific temperature of the 2D material layer would control surface roughness of the 2D material layer to improve further deposition/transfer of the semiconductor/insulating/conductive materials.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung by performing a heat treatment at specific temperature after transfer of the 2D material as taught by Hong to have the method, wherein the 2-D material channel layer is formed by: performing a first annealing process to reduce a surface roughness of the 2-D material channel layer, to complete remove the polymer residues to improve further deposition/transfer of the semiconductor/insulating/conductive materials (Hong, Abstract, pp. 1, 6-7).
With respect to claim 8, Tung discloses a method (e.g., forming field-effect bottom-gate transistor, see the annotated Fig. 10 above) (Tung, Figs. 10, 17, ¶0031, ¶0046, ¶0055-¶0058), comprising:
forming a gate electrode (1014, HfO2) (Tung, Fig. 10, ¶0046) in contact with a gate dielectric layer (1004, HfO2);
forming a 2-D material channel layer (120, MoS2) (Tung, Fig. 10, ¶0046, ¶0055-¶0057) over the first 2-D material buffer layer (e.g., 1006, hBN), wherein the 2-D material channel layer (120) is formed by:
forming the 2-D material channel layer (120) (Tung, Fig. 10, ¶0046, ¶0055-¶0057) on a first carrier (100);
transferring the 2-D material channel layer (120) from the first carrier to the gate dielectric layer (1004) (Tung, Fig. 10, ¶0046, ¶0057); and
forming source/drain electrodes (1010/1012) (Tung, Fig. 10, ¶0046, ¶0057) over source/drain regions of the 2-D material channel layer (120, MoS2).
Further, Tung does not specifically disclose performing a first annealing process to reduce a surface roughness of the 2-D material channel layer.
However, Hong teaches a method of transferring 2D material (e.g., graphene) (Hong, Figs. 3(a)-3(c), Abstract, pp. 1-9) on a SiO2/Si substrate by using polymer layer (e.g., PMMA), and performing a heat treatment at specific temperature (e.g., 500º C) after transfer of the 2D material to remove polymer residues form the surface of the 2D material, wherein after heat treatment the surface roughness (Hong, Figs. 3(a)-3(c), pp. 6-7) of the 2D material decreases due to complete removal of the polymer residues. Thus, a person of ordinary skill in the art would recognize that heat treatment (annealing) of the 2D material layer would control surface roughness of the 2D material layer to improve further deposition/transfer of the semiconductor/
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insulating/conductive materials.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung by performing a heat treatment at specific temperature after transferring the 2D material as taught by Hong to have the method, comprising: performing a first annealing process to reduce a surface roughness of the 2-D material channel layer, to completely remove the polymer residues to improve further deposition/transfer of the semiconductor/insulating/conductive materials (Hong, pp. 1, 6-7).
Regarding claim 9, Tung in view of Hong discloses the method of claim 8. Further, Tung discloses the method, further comprising forming a 2-D material buffer layer (e.g., hBN monolayer 1006) (Tung, Fig. 10, ¶0046, ¶0057) over the gate dielectric layer (1004) prior to forming the 2-D material channel layer (120), wherein the 2-D material channel layer (120) is formed in contact with the 2-D material buffer layer (1006).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Hong (KR 20130026679 A) as applied to claim 5, and further in view of Shepard (US 2016/0240692).
Regarding claim 6, Tung in view of Hong discloses the method of claim 5. Further, Tung does not specifically disclose the method, wherein the first 2-D material buffer layer is formed by: performing a second polydimethylsiloxane (PDMS) stamping process to transfer the first 2-D material buffer layer to the gate dielectric layer; and performing a second annealing process to reduce a surface roughness of the first 2-D material buffer layer.
However, Shepard teaches forming a hetero-structure (e.g., 206/202/204 or 608/602/606) (Shepard, Figs. 2, 4, 6, ¶0007-¶0014, ¶0055-¶0079, ¶0097) comprising a 2-D material layer (202 or 602) (Shepard, Figs. 2, 4, 6, ¶0057-¶0059) including graphene or MoS2 material layer encapsulated between a first buffer layer (206 or 608) and a second buffer layer (204 or 606) comprised of hexagonal boron nitride (hBN) or other 2-D material that is different from the 2-D material layer (202 or 602), to reduce environmental sensitivity, to control band structure, and to provide 2D FETs having high mobility (Shepard, ¶0048, ¶0075-¶079, ¶0097).
The hetero-structure (e.g., 206/202/204 or 608/602/606) (Shepard, Figs. 2, 4, 6, ¶0007-¶0014, ¶0055-¶0079, ¶0097) is formed by performing a plurality of polydimethylsiloxane (PDMS) stamping processes comprising performing a second polydimethylsiloxane (PDMS) stamping process (e.g., at 408/410) to transfer the first 2-D material buffer layer (e.g., bottom hBN) (Shepard, Fig. 4, ¶0069) to the gate dielectric layer (e.g., the substrate including a gate dielectric layer).
Further, Hong teaches performing a heat treatment at specific temperature to complete remove the polymer residues after transfer of the 2D material layer, wherein the surface roughness (Hong, Figs. 3(a)-3(c), pp. 6-7) of the 2D material decreases due to complete removal of the polymer residues. Thus, a person of ordinary skill in the art would recognize that heat treatment at specific temperature of the 2D material buffer layer would control surface roughness of the 2D material buffer layer to improve further deposition/transfer of the semiconductor/insulating/conductive materials.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung/Hong by forming a hetero-structure comprising a 2-D material layer encapsulated between a first buffer layer and a second buffer layer as taught by Shepard, wherein a heat treatment at specific temperature is performed after transfer of the 2D material layer as taught by Hong to have the method, wherein the first 2-D material buffer layer is formed by: performing a second polydimethylsiloxane (PDMS) stamping process to transfer the first 2-D material buffer layer to the gate dielectric layer; and performing a second annealing process to reduce a surface roughness of the first 2-D material buffer layer, in order to reduce environmental sensitivity of the channel layer, and to provide 2D FET having high mobility; and to complete remove the polymer residues to improve further deposition/transfer of the semiconductor/insulating/conductive materials (Shepard, ¶0004, ¶0007-¶0014, ¶0048, ¶0057-¶0059, ¶0075-¶079, ¶0097; Hong, Abstract, pp. 1, 6-7).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Cho et al. (US 2015/0280011, hereinafter Cho).
Regarding claim 7, Tung discloses the method of claim 1. Further, Tung does not specifically disclose the method, further comprising forming a passivation layer covering a top surface of the 2-D material channel layer after forming the source/drain electrodes.
However, Cho teaches forming a passivation layer (460) (Cho, Figs. 4A-4C, ¶0024-¶0026, ¶0048-¶0072) covering a top surface of the 2-D material channel layer (e.g., graphene channel layer 410) (Cho, Fig. 4C, ¶0061-¶0063) after forming the source/drain electrodes (420/430), to suppress the deterioration of the channel layer properties under external condition to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0061, ¶0072).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung by forming a passivation layer on the 2-D material channel layer and the source/drain electrodes as taught by Cho to have the method, further comprising forming a passivation layer covering a top surface of the 2-D material channel layer after forming the source/drain electrodes, in order to suppress the deterioration of the channel layer properties under external condition to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0061, ¶0072).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Hong (KR 20130026679 A) as applied to claim 8, and further in view of Lin (US 2017/0345944).
Regarding claim 10, Tung in view of Hong discloses the method of claim 8. Further, Tung does not specifically disclose the method, further comprising forming a 2-D material buffer layer over the 2-D material channel layer after forming the source/drain electrodes.
However, Lin teaches the method comprising after forming the source/drain electrodes (Lin, Figs. 3A, 4A, 12A, ¶0028, ¶0040, ¶0046, ¶0049), forming a 2-D material buffer layer (e.g., 182, the second buffer layer 182 and gate stack 120 are collectively patterned to form a stack between the source/drain electrodes 112/114 after forming the source/drain electrodes 112/114, as in Figs. 3A-4A) over the 2-D material channel layer (108), to provide a hetero-structure FET with minimized vertical sizes and enhanced electrical performance (Lin, ¶0014, ¶0046, ¶0049).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung/Hong by forming a 2-D material buffer layer over the 2-D material channel layer as taught by Lin to have the method, further comprising forming a 2-D material buffer layer over the 2-D material channel layer after forming the source/drain electrodes, in order to provide improved hetero-structure FET with minimized vertical sizes and enhanced electrical performance (Lin, ¶0014, ¶0046, ¶0049).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Hong (KR 20130026679 A) as applied to claim 8, and further in view of Cho (US 2015/0280011).
Regarding claim 11, Tung in view of Hong discloses the method of claim 8. Further, Tung does not specifically disclose the method, further comprising forming a dielectric passivation layer covering a top surface of the 2-D material channel layer after forming the source/drain electrodes.
However, Cho teaches forming a passivation layer (460) (Cho, Figs. 4A-4C, ¶0024-¶0026, ¶0048-¶0072) covering a top surface of the 2-D material channel layer (e.g., graphene channel layer 410) (Cho, Fig. 4C, ¶0061-¶0063) after forming the source/drain electrodes (420/430), to suppress the deterioration of the channel layer properties under external condition to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0061, ¶0072).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung/Hong by forming a passivation layer on the 2-D material channel layer and the source/drain electrodes as taught by Cho to have the method, further comprising forming a dielectric passivation layer covering a top surface of the 2-D material channel layer after forming the source/drain electrodes, in order to suppress the deterioration of the channel layer properties under external condition to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0061, ¶0072).
Regarding claim 12, Tung in view of Hong discloses the method of claim 8. Further, Tung does not specifically disclose the method, further comprising performing a first patterning process to an exposed portion of the 2-D material channel layer after forming the source/drain electrodes, so as to narrow down the 2-D material channel layer along a first direction.
However, Cho teaches the method comprising performing a first patterning process (e.g., step S230) to an exposed portion of the 2-D material channel layer (Cho, Fig. 4A, ¶0054-¶0055, ¶0061, ¶0072) after forming the source/drain electrodes (e.g., step S220), so as to provide a channel having a desired width and length.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung/Hong by patterning the 2-D material channel layer after forming the source/drain electrodes as taught by Cho to have the method, further comprising performing a first patterning process to an exposed portion of the 2-D material channel layer after forming the source/drain electrodes, so as to narrow down the 2-D material channel layer along a first direction, in order to provide a channel having a desired width and length to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0055, ¶0072).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Hong (KR 20130026679 A) and Cho (US 2015/0280011) as applied to claim 12, and further in view of Choi et al. (US 2016/0093491, hereinafter Choi) and Choi et al. (US 2008/0296558, hereinafter Choi’558).
Regarding claim 13, Tung in view of Hong and Cho discloses the method of claim 12. Further, Tung does not specifically disclose the method, further comprising performing a second patterning process to the source/drain electrodes prior to performing the first patterning process, such that each of the source/drain electrodes comprise a main portion and a protruding portion extending from the main portion along a second direction perpendicular to the first direction.
However, Choi teaches forming a 2D FET transistor (Choi, Fig. 5a, ¶0007-¶0011, ¶0024-¶0025, ¶0032) comprising MoS2 channel layer and source and drain electrodes over the MoS2 channel layer, wherein each of the source/drain electrodes comprise a main portion and a protruding portion extending from the main portion along a second direction (e.g., a horizontal direction extending between the source electrode and the drain electrode) perpendicular to the first direction, to provide high performance 2D FET transistor having high mobility and on/off ratio.
Further, Choi’558 teaches performing a patterning process to the source/drain electrodes (84) (Choi’558, Fig. 11A-11C, ¶0002, ¶0049-¶0050) such that each of the source/drain electrodes comprise a main portion and a protruding portion extending from the main portion along a second direction perpendicular to the first direction, in order to provide the source/drain electrodes having reduced size for the nano-sale transistors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung/Hong/Cho by forming the source/drain electrodes by patterning as taught by Choi and Choi’558 to have the method, further comprising performing a second patterning process to the source/drain electrodes prior to performing the first patterning process, such that each of the source/drain electrodes comprise a main portion and a protruding portion extending from the main portion along a second direction perpendicular to the first direction, in order to provide high performance 2D FET transistor having high mobility and on/off ratio; and to provide the source/drain electrodes having reduced size for the nano-sale transistors (Choi, ¶0007-¶0011, ¶0024-¶0025, ¶0032; Choi’558, ¶0002, ¶0049).
Regarding claims 14 and 15, Tung in view of Hong, Cho, Choi, and Choi’558 discloses the method of claim 13. Further, Tung does not specifically disclose the method, wherein after the first patterning process is complete, the 2-D material channel layer has a channel region between the source/drain electrodes, and a source/drain region below the protruding portion of one of the source/drain electrodes, wherein the channel region is wider than the source/drain region along the first direction (as claimed in claim 14); wherein the protruding portion is narrower than the main portion along the first direction (as claimed in claim 15).
However, Cho teaches that the first patterning process (e.g., step S230) to an exposed portion of the 2-D material channel layer (Cho, Fig. 4A, ¶0054-¶0055, ¶0061, ¶0072) provides a channel having a desired width and length.
Further, Choi teaches forming the source and drain electrodes (Choi, Fig. 5a, ¶0032) over the MoS2 channel layer, such that the 2-D material channel layer has a channel region between the source/drain electrodes, and a source/drain region below the protruding portion of one of the source/drain electrodes, wherein the channel region is wider than the source/drain region along the first direction; and the protruding portion of the source/drain electrodes is narrower than the main portion along the first direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung/Hong/Cho/Choi/Choi’558 by patterning the 2-D material channel layer after forming the source/drain electrodes as taught by Cho, wherein the source/drain electrodes are formed by patterning as taught by Choi/Choi’558 to have the method, wherein after the first patterning process is complete, the 2-D material channel layer has a channel region between the source/drain electrodes, and a source/drain region below the protruding portion of one of the source/drain electrodes, wherein the channel region is wider than the source/drain region along the first direction (as claimed in claim 14); wherein the protruding portion is narrower than the main portion along the first direction (as claimed in claim 15), in order to provide a channel having a desired width and length to obtain a back-gate transistor having stable operation; to provide high performance 2D FET transistor having high mobility and on/off ratio; and to provide the source/drain electrodes having reduced size for the nano-sale transistors (Cho, ¶0024-¶0026, ¶0055, ¶0072; Choi, ¶0007-¶0011, ¶0024-¶0025, ¶0032; Choi’558, ¶0002, ¶0049).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Lin (US 2017/0345944).
Regarding claim 23, Tung discloses the method of claim 21. Further, Tung does not specifically disclose the method, further comprising, after forming the source/drain electrodes, forming a 2-D material buffer layer over the 2-D material channel layer.
However, Lin teaches the method comprising after forming the source/drain electrodes (Lin, Figs. 3A, 4A, 12A, ¶0028, ¶0040, ¶0046, ¶0049), forming a 2-D material buffer layer (e.g., 182, the second buffer layer 182 and gate stack 120 are collectively patterned to form a stack between the source/drain electrodes 112/114 after forming the source/drain electrodes 112/114, as in Figs. 3A-4A) over the 2-D material channel layer (108), to provide a hetero-structure FET with minimized vertical sizes and enhanced electrical performance (Lin, ¶0014, ¶0046, ¶0049).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung by forming a 2-D material buffer layer over the 2-D material channel layer as taught by Lin to have the method, further comprising, after forming the source/drain electrodes, forming a 2-D material buffer layer over the 2-D material channel layer, in order to provide improved hetero-structure FET with minimized vertical sizes and enhanced electrical performance (Lin, ¶0014, ¶0046, ¶0049).
Claims 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0335587 to Tung in view of Lin (US 2017/0345944) as applied to claim 23, and further in view of Cho (US 2015/0280011).
Regarding claim 24, Tung in view of Lin discloses the method of claim 23. Further, Tung does not specifically disclose the method, wherein the second 2-D material buffer layer interfaces with the source/drain electrodes.
However, Cho teaches forming a passivation layer (460) (Cho, Figs. 4A-4C, ¶0024-¶0026, ¶0048-¶0072) covering a top surface of the 2-D material channel layer (e.g., graphene channel layer 410) (Cho, Fig. 4C, ¶0061-¶0063) after forming the source/drain electrodes (420/430), and the passivation layer (460) includes boron nitride material, such that the passivation layer (460) interfaces with the source/drain electrodes (420/430), to suppress the deterioration of the channel layer properties under external condition to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0061, ¶0072).
Further, Tung teaches that hexagonal boron nitride (hBN) (Tung, ¶0054) is an insulator material that is covalently bonded monolayer to provide high flexibility 2D electronic devices.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung/Lin by forming a passivation layer on the 2-D material channel layer and the source/drain electrodes as taught by Cho, wherein the passivation layer includes hexagonal boron nitride (hBN) material to have the method, wherein the second 2-D material buffer layer interfaces with the source/drain electrodes, in order to suppress the deterioration of the channel layer properties under external condition, to protect the 2D FET, and to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0061, ¶0072; Tung, ¶0054).
Regarding claim 25, Tung in view of Lin discloses the method of claim 23. Further, Tung does not specifically disclose the method, further comprising forming a passivation layer over the second 2-D material buffer layer.
However, Cho teaches forming a passivation layer (460) (Cho, Figs. 4A-4C, ¶0024-¶0026, ¶0048-¶0072) covering a top surface of the 2-D material channel layer (e.g., graphene channel layer 410) (Cho, Fig. 4C, ¶0061-¶0063) after forming the source/drain electrodes (420/430), to suppress the deterioration of the channel layer properties under external condition to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0061, ¶0072).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Tung/Lin by forming a passivation layer on the 2-D material channel layer and the source/drain electrodes as taught by Cho to have the method, further comprising forming a passivation layer over the second 2-D material buffer layer, in order to suppress the deterioration of the channel layer properties under external condition, to protect the 2D FET, and to obtain a back-gate transistor having stable operation (Cho, ¶0024-¶0026, ¶0061, ¶0072).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891