DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF JAPAN on 12/20/2022.
Election/Restrictions
Applicant's election without traverse of “Species A (Claims 1-7 and 9-13)” in the reply filed on January 26, 2026, is acknowledged.
Claim 8 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 10-11 are rejected under 35 U.S.C. 103 as being obvious over US 2019/0326316 A1; Son et al.; 10/2019; (“316”) in view of US 12,075,624 B2; Baek et al.; 08/2024; (“624”).
Regarding Claim 1. 316 teaches in Figs. 2A and 3A about a semiconductor storage device, comprising:
a layered body (“memory cell block may include a plurality of gate electrodes 485 spaced apart from each other in the first direction, first insulation patterns 315 between neighboring ones of the gate electrodes 485”, [0038], Ln. 1-4) including a plurality of gate electrode layers (Fig. 2A, items 485) and a plurality of first insulating layers (Fig. 2A, items 315) alternately stacked on top of one another in a first direction (Fig. 2A, items 315 and 485 are stacked alternately in a first direction);
a first columnar body (see annotated by Examiner Fig. 3A, item 510) extending in the first direction; and
a second columnar body (see annotated by Examiner Fig. 3A, item 510) extending in the first direction, wherein
the gate electrode layers include a first gate electrode layer (see annotated by Examiner Fig. 3A, item 485), and a second gate electrode layer (see annotated by Examiner Fig. 3A, item 485) that is disposed on a first side in the first direction with respect to the first gate electrode layer (Fig. 3A, second gate electrode layer disposed on top of first gate electrode layer), and the second gate layer has a length in a second direction that intersects the first direction that is less than a length of the first gate electrode layer in the second direction (Fig. 3A, length in a second direction of the second gate layer is less than the length of the first gate layer, in the same direction),
the first columnar body includes a first conductive portion (see annotated by Examiner Fig. 3A, first columnar item 510) that penetrates the first gate electrode layer in the first direction and is electrically connected to the first gate electrode layer (see annotated by Examiner Fig. 3A, first columnar item 510 penetrates and electrically connects to the first gate electrode layer 485),
the second columnar body includes a second conductive portion (see annotated by Examiner Fig. 3A, second columnar item 510) that penetrates the second gate electrode layer and the first gate electrode layer in the first direction and is electrically connected to the second gate electrode layer (see annotated by Examiner Fig. 3A, second columnar item 510 penetrates first and second gate electrode layers, also second columnar item 510 electrically connects to the second gate electrode layer 485), and an insulating portion disposed between the first gate electrode layer and the second conductive portion (see annotated by Examiner Fig. 3A, insulating portion items 505).
316 does not teach about a semiconductor storage device, comprising:
the first gate electrode layer includes a barrier metal film, and
at least one end portion in the second direction of the barrier metal film is positioned between at least one portion of the first conductive portion and the second conductive portion with regard to the second direction, and extends in a third direction that intersects the first direction and the second direction.
624 teaches in Fig. 4B about a semiconductor storage device, comprising:
the columnar bodies include a barrier metal film (item BM), and
at least one end portion in the second direction of the barrier metal film is positioned between at least one portion of the first conductive portion and the second conductive portion with regard to the second direction (at least one end portion of item BM, in the second direction, is positioned between one portion of the first and second conductive portions), and extends in a third direction that intersects the first direction and the second direction (item BM extends in a third direction).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the barrier metal film of 624 to be positioned between the electrode layers and the columnar bodies in 316 in order to provide “a diffusion break layer BM that covers a surface of the main contact part MP” or columnar bodies as taught by 624 in Fig. 4B and Col. 13, Ln. 8-9.
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Excerpt of Fig. 3A, annotated by Examiner from Son et al. “316”
Regarding Claim 2. 316 teaches in Fig. 3A about a semiconductor storage device, comprising:
wherein the first gate electrode layer includes a terraced portion (see annotated by Examiner Fig. 3A) that does not coincide with the second gate electrode layer (see annotated by Examiner Fig. 3A, first gate electrode layer terraced portion does not coincide with the second gate electrode layer) and a non-terraced portion (see annotated by Examiner Fig. 3A) that coincides with the second gate electrode layer (see annotated by Examiner Fig. 3A, first gate electrode layer non-terraced portion coincides with the second gate electrode layer), and
a thickness in the first direction of the terraced portion and a thickness in the first direction of the non-terraced portion are not identical to each other.
316 does not teach about a semiconductor storage device, comprising:
a thickness in the first direction of the terraced portion and a thickness in the first direction of the non-terraced portion are identical to each other.
It would have been an obvious matter of design choice to provide the terraced and non-terraced portions of the gate electrode layers with identical thicknesses, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 3. 316 teaches in Fig. 3A about a semiconductor storage device, comprising:
wherein the first gate electrode layer includes a terraced portion that does not coincide with the second gate electrode layer, and
the thickness in the first direction of the terraced portion and a thickness in the first direction of the insulating portion (Fig. 3A, thickness in the first direction of item 505) are not identical to each other.
316 does not teach about a semiconductor storage device, comprising:
the thickness in the first direction of the terraced portion and a thickness in the first direction of the insulating portion are identical to each other.
It would have been an obvious matter of design choice to provide the terraced portions and the insulating portions of the gate electrode layers with identical thicknesses, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 4. 316 teaches in Fig. 3A about a semiconductor storage device, comprising:
wherein a thickness in the second direction of the insulating portion is not disclosed.
316 does not teach about a semiconductor storage device, comprising:
wherein a thickness in the second direction of the insulating portion is equal to or greater than about 20nm.
It would have been an obvious matter of design choice to provide the insulating portions of the gate electrode layers with a thickness necessary to provide proper insulation characteristics, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 5. 316 teaches in Figs. 3A and 3C about a semiconductor storage device, comprising:
wherein at least one portion (Fig. 3A, penetrating portion shown in claim 1 that extends in the positive and negative second direction from the conductive portions; also shown in Fig. 3C as item 510B) of the second conductive portion is positioned nearer than an end in the second direction of the second gate electrode layer to the first conductive portion (Fig. 3C, item 510B of the second conductive portion is closer in the second direction to the first conductive portion than the second gate electrode layer).
Regarding Claim 10. 316 teaches in Figs. 2A and 3A about a semiconductor storage device, comprising:
a layered body (“memory cell block may include a plurality of gate electrodes 485 spaced apart from each other in the first direction, first insulation patterns 315 between neighboring ones of the gate electrodes 485”, [0038], Ln. 1-4) including a plurality of gate electrode layers (Fig. 2A, items 485) and a plurality of first insulating layers (Fig. 2A, items 315) alternately stacked in a first direction (Fig. 2A, items 315 and 485 are stacked alternately in a first direction);
a first columnar body extending in the first direction; and
a second columnar body extending in the first direction, wherein
the gate electrode layers include a first gate electrode layer (see annotated by Examiner Fig. 3A, item 485), and a second gate electrode layer (see annotated by Examiner Fig. 3A, item 485) that is disposed on a first side in the first direction with respect to the first gate electrode layer (Fig. 3A, second gate electrode layer disposed on top of first gate electrode layer), and the second gate electrode layer has a length in a second direction that intersects the first direction less than a length of the first gate electrode layer in the second direction (Fig. 3A, length in a second direction of the second gate layer is less than the length of the first gate layer, in the same direction),
the first gate electrode layer includes a terraced portion (see annotated by Examiner Fig. 3A) that does not coincide with the second gate electrode layer (see annotated by Examiner Fig. 3A, first gate electrode layer terraced portion does not coincide with the second gate electrode layer) and a non-terraced portion (see annotated by Examiner Fig. 3A) that coincides with the second gate electrode layer (see annotated by Examiner Fig. 3A, first gate electrode layer non-terraced portion coincides with the second gate electrode layer),
the first columnar body includes a first conductive portion (see annotated by Examiner Fig. 3A, first columnar item 510) that penetrates the terraced portion of the first gate electrode layer in the first direction and is electrically connected to the first gate electrode layer (see annotated by Examiner Fig. 3A, first columnar item 510 penetrates the terraced portion of the first gate electrode and electrically connects to the first gate electrode layer 485),
the second columnar body includes a second conductive portion (see annotated by Examiner Fig. 3A, second columnar item 510) that penetrates the second gate electrode layer and the non-terraced portion of the first gate electrode layer in the first direction and is electrically connected to the second gate electrode layer (see annotated by Examiner Fig. 3A, second columnar item 510 penetrates in the first direction the second gate electrode and the non-terraced portion of the first gate electrode layer, also second columnar item 510 electrically connects to the second gate electrode layer 485), and an insulating portion disposed between the non-terraced portion of the first gate electrode layer and the second conductive portion (see annotated by Examiner Fig. 3A, insulating portion items 505), and
a thickness in the first direction of the terraced portion and a thickness in the first direction of the non-terraced portion are not identical to each other.
316 does not teach about a semiconductor storage device, comprising:
a thickness in the first direction of the terraced portion and a thickness in the first direction of the non-terraced portion are identical to each other.
It would have been an obvious matter of design choice to provide the terraced and non-terraced portions of the gate electrode layers with identical thicknesses, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding Claim 11. 316 teaches in Figs. 9,11,22-23,28 and 32 about a semiconductor storage device, comprising:
forming a layered body including a plurality of first sacrificial layers (Fig. 9, items 320) and a plurality of first insulating layers (Fig. 9, items 310) alternately stacked on top of one another in a first direction (Fig. 9, items 310 and 320 are alternately stacked in a first direction);
forming a stepped region wherein respective lengths of the first sacrificial layers in a second direction that intersects the first direction differ from one another (Fig. 11, at least seven stepped regions are shown, wherein the lengths of the first sacrificial layers differ from one another);
etching the stepped region (“sacrificial layers 320 thereunder may be etched”, [0089], Ln. 5-6), and removing end portions of the first sacrificial layers, thereby forming a plurality of first space portions corresponding to the removed end portions of the first sacrificial layers (Fig. 22, at least end portion items 464 and 466 are removed from the first sacrificial layers);
forming a plurality of holes that penetrate the first sacrificial layers in the first direction in the stepped region (Fig. 22, opening items 454 fully penetrate the first sacrificial layers in the first direction in the stepped region);
etching through the holes, and removing one portion of the first sacrificial layers exposed by the holes, thereby forming a plurality of second space portions (Fig 22, etching through items 454 to form horizontal portion items 464 and 466) corresponding to the removed one portion of the first sacrificial layers (Fig. 22, at least end portion items 464 and 466 correspond to the removed one portion of the first sacrificial layers);
forming a plurality of insulating portions (Fig. 28, items 505) in the second space portions (Fig. 22, shows that items 505 are formed within items 464 or 466 which are not only located at the ends of the electrode layers);
replacing the first sacrificial layers with a plurality of conductive layers (Fig. 23, layer items 480 replace sacrificial layer items 320); and
forming a plurality of conductive portions in the first space portions and the holes (Fig. 32, conductive portion items 510b and 510a are formed in the first space portions and holes respectively).
Allowable Subject Matter
Claims 6-7,9 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897