DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 10-12, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ge et al. (U.S. Patent Application Publication No. 2025/0006596).
Regarding to claim 1, Ge teaches a semiconductor package, comprising:
a semiconductor die having a device side in which circuitry is formed (Figs. 1-2, element 30; [0028], lines 5-8, semiconductor die 30 having a device side, which is the top side, in which circuitry is formed, including pads 32);
a conductive terminal coupled to the device side of the semiconductor die (Figs. 1-2, element 20; [0028], line 5, conductive terminal 20 is coupled to the device side of the semiconductor die 30 by wire 33); and
a mold compound covering the semiconductor die and at least part of the conductive terminal, the conductive terminal exposed to an exterior of the mold compound (Figs. 1-2, element 40; [0029], lines 1-2, mold compound 40 covering the semiconductor die 30 and at least part of the conductive terminal 20, the conductive terminal 20 exposed to an exterior of the mold compound 40),
wherein the mold compound has top (Figs. 1-2, surface 41) and bottom surfaces (Figs. 1-2, surface 45) and a lateral side extending between the top and bottom surfaces, the lateral side including:
a first surface contacting the top surface and extending vertically from the top surface toward the bottom surface (Figs. 1-2, surface 43),
a second surface contacting the first surface and extending horizontally away from the semiconductor die (Figs. 1-2, surface 46), and
a third surface contacting the second surface and extending from the second surface to contact the bottom surface (Figs. 1-2, surface 44), the third surface having physical marks resulting from a singulation process, the first and second surfaces lacking physical marks resulting from the singulation process (Fig. 4, step S104, the singulation is made to form the third surface 44, therefore the third surface 44 having physical marks resulting from a singulation process. This singulating process does not touch the first surface 43 or the second surface 46, thus the first and second surfaces lacking physical marks resulting from the singulation process).
Regarding to claim 3, Ge teaches the singulation process is a mechanical sawing process. ([0015], last 2 lines, mechanical sawing process).
Regarding to claim 4, Ge teaches the first surface is not normal to the second surface (Fig. 2, the first surface 43 is not normal to the second surface 46).
Regarding to claim 5, Ge teaches a height of the third surface is less than a height of the package (Fig. 1, [0030], last 2 lines).
Regarding to claim 10, Ge teaches a semiconductor package, comprising:
a semiconductor die having a device side in which circuitry is formed (Figs. 1-2, element 30; [0028], lines 5-8, semiconductor die 30 having a device side, which is the top side, in which circuitry is formed, including pads 32);
a conductive terminal coupled to the device side of the semiconductor die (Figs. 1-2, element 20; [0028], line 5, conductive terminal 20 is coupled to the device side of the semiconductor die 30 by wire 33); and
a mold compound covering the semiconductor die and at least part of the conductive terminal, the conductive terminal exposed to an exterior of the mold compound (Figs. 1-2, element 40; [0029], lines 1-2, mold compound 40 covering the semiconductor die 30 and at least part of the conductive terminal 20, the conductive terminal 20 exposed to an exterior of the mold compound 40),
wherein the mold compound includes a lateral surface extending in a vertical direction and having a height less than a height of the package (Figs. 1-2, surface 44), the lateral surface having physical marks resulting from a singulation process (Fig. 4, step S104, the singulation is made to form the surface 44, therefore the surface 44 having physical marks resulting from a singulation process.).
Regarding to claim 11, Ge teaches the mold compound includes a lateral side comprising:
a first surface contacting a top surface of the package and extending vertically toward a bottom surface of the package (Figs. 1-2, surface 43);
a second surface contacting the first surface and extending horizontally away from the semiconductor die (Figs. 1-2, surface 46); and
the lateral surface contacting the second surface and extending vertically to contact the bottom surface of the package (Figs. 1-2, surface 44).
Regarding to claim 12, Ge teaches the first surface is not normal to the second surface (Fig. 2, the first surface 43 is not normal to the second surface 46).
Regarding to claim 16, Ge teaches the singulation process is a mechanical sawing process ([0015], last 2 lines, mechanical sawing process).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jaurigue et al. (U.S. Patent No. 9,012,268) in view of Kwon et al. (U.S. Patent Application Publication No. 2021/0143073).
Regarding to claim 17, Jaurigue teaches method for manufacturing a semiconductor package, comprising:
coupling multiple semiconductor dies to multiple die pads of a high-density lead frame (Figs. 4A-B, column 5, lines 50-51, coupling multiple semiconductor dies 32 to multiple die pads 12 of a high-density lead frame);
coupling each of the multiple semiconductor dies to conductive terminals of the high-density lead frame (Fig. 4C, column 5, lines 56-57, coupling each of the multiple semiconductor dies 32 to conductive terminals 74 of the high-density lead frame);
positioning the high-density lead frame and the semiconductor dies in a mold chase. causing mold compound to cover the semiconductor dies in the mold chase (Fig. 4D, column 6, lines 14-16, positioning the high-density lead frame and the semiconductor dies in a mold chase to form mold 44);
removing the high-density lead frame from the mold chase (Fig. 4E);
trimming the high-density lead frame (Fig. 4F, column 6, lines 43-45); and
singulating the mold compound-covered multiple semiconductor dies from each other to produce semiconductor packages, wherein the singulation is performed by using a tool to cut through the portions of the mold compound between the semiconductor dies (Fig. 4G, column 6, lines 64-66).
Jaurigue does not disclose the mold chase having protrusions positioned between consecutive ones of the multiple die pads, the mold compound flow underneath the protrusions in the mold chase, wherein portions of the mold compound covering the semiconductor dies are thicker than portions of the mold compound between the semiconductor dies.
Kwon discloses a mold chase having protrusions positioned between consecutive ones of the multiple dies, the mold compound flow underneath the mold chase, portions of the mold compound covering semiconductor dies are thicker than portions of the mold compound between semiconductor dies (Fig. 2A-B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jaurigue in view of Kwon to position protrusions in the mold chase between consecutive ones of the multiple die pads, and to have the mold compound flowing underneath the protrusions in the mold chase, and as a result, portions of the mold compound covering the semiconductor dies are thicker than portions of the mold compound between the semiconductor dies, in order to provide an opening for the subsequent singulation process. This would reduce contaminations during sawing.
Regarding to claim 18, Kwon discloses the protrusions include first bottom surfaces and further include pillars having second bottom surfaces (Fig. 2A). Jaurigue as modified in view of Kwon causes the second bottom surfaces extending closer to the lead frame than do the first bottom surfaces.
Regarding to claim 19, Kwon discloses the pillars produce cavities that are coincident with multiple surfaces of the semiconductor packages (Fig. 3, cavities 142 produced by the pillar 116 coincident with multiple surfaces of the semiconductor packages).
Regarding to claim 20, Jaurigue teaches the tool is a laser or mechanical saw (column 6, lines 64-65).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. (U.S. Patent Application Publication No. 2025/0006596), as applied to claim 1 above, in view of Jaurigue et al. (U.S. Patent No. 9,012,268).
Regarding to claim 2, Ge discloses the singulation process is a sawing process ([0015], last 2 line). However, Ge does not disclose the sawing process is a laser sawing process. Jaurigue disclose a singulation process is a laser sawing process (column 6, lines 64-65). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ge in view of Jaurigue to use a laser sawing process for singulating in order to increase accuracy and reduce contaminations.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. (U.S. Patent Application Publication No. 2025/0006596), as applied to claim 1 above.
Regarding to claim 6, Ge teaches a die pad coupled to the semiconductor die (Fig. 1, element 10), wherein an edge of the die pad is within a distance from a closest edge of the bottom surface (Fig. 1). Ge does not disclose a range of the distance, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure an edge of the die pad to be within 0.5 mm from a closest edge of the bottom surface in order to reduce footprint, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. (U.S. Patent Application Publication No. 2025/0006596), as applied to claim 10 above, in view of Jaurigue et al. (U.S. Patent No. 9,012,268).
Regarding to claim 15, Ge discloses the singulation process is a sawing process ([0015], last 2 line). However, Ge does not disclose the sawing process is a laser sawing process. Jaurigue disclose a singulation process is a laser sawing process (column 6, lines 64-65). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ge in view of Jaurigue to use a laser sawing process for singulating in order to increase accuracy and reduce contaminations.
Allowable Subject Matter
Claims 7-9 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 7, the prior art fails to anticipate or render obvious the claimed limitations including “a cavity in the lateral side, a floor of the cavity lying in a first horizontal plane that is between a second horizontal plane coincident with the bottom surface and a third horizontal plane coincident with the second surface” in combination with the limitations recited in claim 1.
Regarding to claim 13, the prior art fails to anticipate or render obvious the claimed limitations including “a cavity in the lateral side, the cavity having a floor coincident with a first horizontal plane that lies between a second horizontal plane coincident with the bottom surface and a third horizontal plane coincident with the second surface” in combination with the limitations recited in claims 10-11.
Pertinent Art
For the benefits of the Applicant, US-10083866-B2, US-10109564-B2, US-9935250-B2, US-10418294-B1, US-12224232-B2, US-7030469-B2, US-7863730-B2, and US-6841414-B1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. In particular, Fig. 1F in the US-10109564-B2, and Fig. 4A-B in the US-12224232-B2 discloses the features of independent claims 1 and 10, and some of their dependent claims.
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Other references disclose most features of the claims but fail to disclose the combination of limitations including “a third surface contacting the second surface and extending from the second surface to contact the bottom surface, the third surface having physical marks resulting from a singulation process, the first and second surfaces lacking physical marks resulting from the singulation process, a cavity in the lateral side, a floor of the cavity lying in a first horizontal plane that is between a second horizontal plane coincident with the bottom surface and a third horizontal plane coincident with the second surface” or “positioning the high-density lead frame and the semiconductor dies in a mold chase, the mold chase having protrusions positioned between consecutive ones of the multiple die pads; causing mold compound to cover the semiconductor dies in the mold chase and flow underneath the protrusions in the mold chase, wherein portions of the mold compound covering the semiconductor dies are thicker than portions of the mold compound between the semiconductor dies.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897