Prosecution Insights
Last updated: July 15, 2026
Application No. 18/459,119

MOLD COMPOUND TRENCHES TO FACILITATE PACKAGE SINGULATION

Non-Final OA §103
Filed
Aug 31, 2023
Examiner
VU, VU A
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Non-Final)
92%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1241 granted / 1344 resolved
+24.3% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
39 currently pending
Career history
1376
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
76.5%
+36.5% vs TC avg
§102
13.4%
-26.6% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1344 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Acknowledgment is made that applicant's Amendment, filed on March 09th, 2026, has been entered. Upon entrance of the Amendment, claims 1, 8, 10, 14, and 17 were amended, claims 7 and 13 were cancelled. Claims 1-6, 8-12, and 14-20 are currently pending. Response to Arguments Applicant’s arguments, filed on March 09th, 2026, with respect to the rejection of claim 17 have been fully considered and are persuasive. The Applicant has argued “a person of ordinary skill in the art would not modify Jaurigue with a mold chase as taught by Kwon. For example, if the mold chase of Jaurigue is modified to have a trench plate 116 (of Kwon), the connecting bar 76 of Jaurigue would block placement of the mold chase (See Fig. 4C/ 4D of Jaurigue). It is noted that the second side panels 114a and the trench plate 116 are of the same length. the second side panels 114a and the trench plate 116 are of the same length. To create a package as in Jaurigue, the mold chase including the trench plate would need to be at the bottom of the intended package, and if modified the connecting bar would block the mold chase positioning rendering the device of Jaurigue inoperable for its intended purposes.” The argument is not persuasive because there are passageways 119 in the protrusions 116 (Kwon, Fig. 2A, [0015], lines 21-24). Therefore, as being modified, the connecting bar would not block the mold chase positioning rendering the device of Jaurigue inoperable as argued. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jaurigue et al. (U.S. Patent No. 9,012,268) in view of Kwon et al. (U.S. Patent Application Publication No. 2021/0143073). Regarding to claim 17, Jaurigue teaches method for manufacturing a semiconductor package, comprising: coupling multiple semiconductor dies to multiple die pads of a lead frame (Figs. 4A-B, column 5, lines 50-51, coupling multiple semiconductor dies 32 to multiple die pads 12 of a high-density lead frame); coupling each of the multiple semiconductor dies to conductive terminals of the lead frame (Fig. 4C, column 5, lines 56-57, coupling each of the multiple semiconductor dies 32 to conductive terminals 74 of the high-density lead frame); positioning the high-density lead frame and the semiconductor dies in a mold chase. causing mold compound to cover the semiconductor dies in the mold chase (Fig. 4D, column 6, lines 14-16, positioning the high-density lead frame and the semiconductor dies in a mold chase to form mold 44); removing the lead frame from the mold chase (Fig. 4E); trimming the lead frame (Fig. 4F, column 6, lines 43-45); and singulating the mold compound-covered multiple semiconductor dies from each other to produce semiconductor packages, wherein the singulation is performed by using a tool to cut through the portions of the mold compound between the semiconductor dies (Fig. 4G, column 6, lines 64-66). Jaurigue does not disclose the mold chase having protrusions positioned between consecutive ones of the multiple die pads, the mold compound flow underneath the protrusions in the mold chase, wherein portions of the mold compound covering the semiconductor dies are thicker than portions of the mold compound between the semiconductor dies. Kwon discloses a mold chase having protrusions positioned between consecutive ones of the multiple dies, the mold compound flow underneath the mold chase, portions of the mold compound covering semiconductor dies are thicker than portions of the mold compound between semiconductor dies (Fig. 2A-B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jaurigue in view of Kwon to position protrusions in the mold chase between consecutive ones of the multiple die pads, and to have the mold compound flowing underneath the protrusions in the mold chase, and as a result, portions of the mold compound covering the semiconductor dies are thicker than portions of the mold compound between the semiconductor dies, in order to provide an opening for the subsequent singulation process. This would reduce contaminations during sawing. Regarding to claim 18, Kwon discloses the protrusions include first bottom surfaces and further include pillars having second bottom surfaces (Fig. 2A). Jaurigue as modified in view of Kwon causes the second bottom surfaces extending closer to the lead frame than do the first bottom surfaces. Regarding to claim 19, Kwon discloses the pillars produce cavities that are coincident with multiple surfaces of the semiconductor packages (Fig. 3, cavities 142 produced by the pillar 116 coincident with multiple surfaces of the semiconductor packages). Regarding to claim 20, Jaurigue teaches the tool is a laser or mechanical saw (column 6, lines 64-65). Reasons for Allowance Claims 1-6, 8-12, and 14-16 are allowed. The following is an examiner’s statement of reasons for allowance: Claim 1 has been amended to include the features of former allowable claim 7. The reasons for allowance of former claim 7 were indicated in the previous Office Action. Regarding to claim 10, the prior art fails to anticipate or render obvious the claimed limitations including “a cavity in the lateral side, the cavity having a floor coincident with a first horizontal plane that lies between a second horizontal plane coincident with the bottom surface and a third horizontal plane coincident with the second surface” in combination with the rest of limitations recited in claim 10. Claims 2-6, 8-9, 11-12, and 14-16 are allowable for same reasons with the claims which they are dependent from. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VU A VU/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Aug 31, 2023
Application Filed
Dec 10, 2025
Non-Final Rejection mailed — §103
Mar 09, 2026
Response Filed
Apr 15, 2026
Final Rejection mailed — §103
Jun 11, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685179
SEMICONDUCTOR PACKAGE AND METHOD FOR MARKING A SEMICONDUCTOR PACKAGE
3y 2m to grant Granted Jul 14, 2026
Patent 12685088
FILM FRAME CARRIER FOR A CURVED WAFER STAGE
3y 5m to grant Granted Jul 14, 2026
Patent 12684775
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
3y 2m to grant Granted Jul 14, 2026
Patent 12677615
METHOD FOR PROCESSING DEVICE WAFER
2y 10m to grant Granted Jul 07, 2026
Patent 12672562
CAVITY-LESS INTERCONNECT COMPONENT ON GLASS CORE
3y 10m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+6.6%)
1y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1344 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month