Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Restriction Requirement mailed on 10/29/2025, the Applicant elected without traverse Group I encompassing claims 1-24. Non-elected Group to encompassing method claims 25-28 has been withdrawn from examination.
Currently, claims 1-28 are pending and the elected claims 1-24 are examined below.
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 6, 14, 15 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2020/0402894 A1 to Luo et al. ("Luo").
Fig. 1 of Luo has been annotated to support the rejection below:
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Regarding independent claim 1, Luo teaches a package (see Fig. 1), comprising:
a semiconductor die 130 (para [0013] - “a second semiconductor die 130”) having a device side 131 including circuitry formed therein (para [0013] - “The first side 131 of the second semiconductor die 130 is electrically connected to the second bottom 127 of the second conductive plate 122 via a second conductive epoxy 132.”):
a substrate 101, 120 (para [0024] - “first subassembly 101…second subassembly 120”) facing and coupled to the device side 131, the substrate 101, 120 including:
first metal layer 124, 122 (para [0012] - “The second subassembly 120 includes a second conductive plate 122 (e.g., copper or aluminum) with a second recess 123, as well as a conductive structure 124 that is electrically isolated from the second conductive plate 122.”) and second metal layer 104, 102, 106 (para [0010] - “The bottom of the example packaged electronic device 100 includes exposed portions of the first conductive plate 102, the first conductive pad 104, and the second conductive pad 106, separated by an electrically insulating packaging material 108 (e.g., molded plastic).”), the first metal layer 124, 122 positioned closer to the device side 131 than the second metal layer 104, 102, 106 and (mechanically) coupled to the second metal layer 104, 102, 106 by way of a via 126 (para [0012] - “an electrically insulating packaging material 126”), the second metal layer 104, 102, 106 having a top surface 107 facing the semiconductor die 130, the top surface 107 including a notch N1 etched therein; and
a dielectric 114 (para [0011] - “Some examples of materials for the first electrically insulating film 114 and other electrically insulating films of various implementations include dry films or liquid photo-imageable films, solder mask photo resist, polyimide materials (e.g., also photo-imageable and can remove unpolymerized material after application, for example, to make a pattern for isolation), and ABF films.”) contacting the notch N1 and at least part of the second metal layer 104, 102, 106 and the via 126; and
a mold compound 126, 116 (para [0012] - “an electrically insulating packaging material 126”; para [0011] - “A first intermediate conductive epoxy 116”) covering the semiconductor die 130 and the substrate 101, 120,
wherein the package includes a lateral surface LS approximately perpendicular to the first metal layer 124, 122 and second metal layer 104, 102, 106 of the substrate 101, 120, and wherein the mold compound 126, 116, the dielectric 114, and the second metal layer 104, 102, 106 are exposed to the lateral surface LS, a segment of the dielectric 114 positioned between the first metal layer 124, 122 and the lateral surface LS, the segment of the dielectric 114 contacting the mold compound 126, 116 at the lateral surface LS.
Regarding claim 2, Luo teaches the at least one of the first metal layer 124, 122 and second metal layer 104, 102, 106 that includes a lateral surface LS2 or LS3 facing the lateral surface LS of the package, and wherein the notch N1 coincides with the top surface 107 and with the lateral surface LS2 or LS3 of the at least one of the first metal layer 124, 122 and second metal layer 104, 102, 106.
Regarding claim 3, Luo teaches the at least one of the first metal layer 124, 122 and second metal layer 104, 102, 106 that includes a bottom surface, and wherein the bottom surface does not have a notch etched therein.
Regarding claim 5, Luo teaches the dielectric 114 that fills the notch N1.
Regarding claim 6, Luo teaches the dielectric 114 that includes Ajinomoto build-up film (ABF) (para [0011] - “Some examples of materials for the first electrically insulating film 114 and other electrically insulating films of various implementations include…ABF films.”).
Regarding independent claim 14, Luo teaches a package (see Fig. 1), comprising:
a semiconductor die 130 (para [0013] - “a second semiconductor die 130”) having a device side 131 including circuitry formed therein (para [0013] - “The first side 131 of the second semiconductor die 130 is electrically connected to the second bottom 127 of the second conductive plate 122 via a second conductive epoxy 132.”);
a substrate 101, 120 (para [0024] - “first subassembly 101…second subassembly 120”) facing and coupled to the device side 131, the substrate 101, 120 including:
first metal layer 124, 122 (para [0012] - “The second subassembly 120 includes a second conductive plate 122 (e.g., copper or aluminum) with a second recess 123, as well as a conductive structure 124 that is electrically isolated from the second conductive plate 122.”) and second metal layer 104, 102, 106 (para [0010] - “The bottom of the example packaged electronic device 100 includes exposed portions of the first conductive plate 102, the first conductive pad 104, and the second conductive pad 106, separated by an electrically insulating packaging material 108 (e.g., molded plastic).”), the first metal layer 124, 122 (mechanically) coupled to the second metal layer 104, 102, 106 by way of a via 126 (para [0012] - “an electrically insulating packaging material 126”), the first metal layer 124, 122 having a top surface 131 facing the die 130, the top surface 131 of the first metal layer 124, 122 including a notch N1b etched therein, the second metal layer 104, 102, 106 having a top surface 107 facing the die 130 and a lateral surface LS1 orthogonal to the top surface 107, the top and lateral surfaces 107, LS1 of the metal layer 104, 102, 106 having a second notch N1 etched therein; and
a dielectric 114 or 114, 134 (para [0011] - “Some examples of materials for the first electrically insulating film 114 and other electrically insulating films of various implementations include dry films or liquid photo-imageable films, solder mask photo resist, polyimide materials (e.g., also photo-imageable and can remove unpolymerized material after application, for example, to make a pattern for isolation), and ABF films.”; para [0013] - “A second electrically insulating film 134”) contacting at least part of the second metal layer 104, 102, 106 and the via 126; and
a mold compound 126 or 126, 116 (para [0012] - “an electrically insulating packaging material 126”; para [0011] - “A first intermediate conductive epoxy 116”) covering the semiconductor die 130 and the substrate 101, 120.
Regarding claim 15, Luo teaches the dielectric 114, 134 that fills the first and second notches N1b, N1.
Regarding claim 19, Luo teaches the dielectric 114, 134 that includes Ajinomoto build-up film (ABF) (para [0011] - “Some examples of materials for the first electrically insulating film 114 and other electrically insulating films of various implementations include…ABF films.”).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 4.
Independent claim 7 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, the substrate further comprising a dielectric covering the first and second metal stacks and contacting the etched notch.
Claims 8-13 are allowed, because they depend from the allowed independent claim 7.
Claim 16 is objected to for depending on a rejected base claim 14, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 14 or the base claim 14 is amended to include all of the limitations of claim 16.
Claim 17 is objected to for depending on a rejected base claim 14, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 14 or the base claim 14 is amended to include all of the limitations of claim 17.
Claim 18 is objected to for depending on a rejected base claim 14, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 14 or the base claim 14 is amended to include all of the limitations of claim 18.
Independent claim 20 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 20, third and fourth metal layers, the third metal layer positioned closer to the device side than the fourth metal layer, the third and fourth metal layers spaced apart from the first and second metal layers, the first metal layer at least partially overlapping the fourth metal layer in the vertical direction, the first and fourth metal layers in different levels of the substrate.
Claims 21-24 are allowed, because they depend from the allowed independent claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2022/0210911 A1 to Luo et al.
Pub. No. US 2021/0035879 A1 to Kessler et al.
Pub. No. US 2020/0357729 A1 to Kim et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 02 February 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status