DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/31/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Pg. 8, line 1, “… mast pattern M …” should read “… mask pattern M …”.
Pg. 13, line 1, “… a second part within the stack ST …” should read “… a second part over the stack ST …”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14, 17 (and claim 18) are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the limitation "the wiring" in line 1. There is insufficient antecedent basis for this limitation in the claim. It is unclear whether the wiring refers to the conductive pattern or other metal lines. As is best understood, “the wiring” appears to be directed to other metal lines (¶¶ [0042, 0053], detailing the wiring 150 and Figs. 10B and 11H). The limitation will be examined as best understood.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-6, 10 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ramaswamy (US 20140361239 A1).
Re: Independent Claim 1, Ramaswamy discloses a manufacturing method comprising:
forming an opening (vias 430, Fig. 4A) within a stack (alternating layers of insulating materials 428 and conductive materials 402, Fig. 4A);
forming a variable resistance layer (storage element material 412, Fig. 4F) within the opening and on the stack;
forming a conductive layer (404, Fig. 4F, ¶ [0063]) on the variable resistance layer (Fig. 4F);
forming a conductive pattern (bit lines 404, ¶ [0063]), comprising a first part within the opening and a second part on the stack (204 over the stack and 206 inside opening 230 in Fig. 2; Fig. 2 describes an orthogonal cross section with respect to Figs. 4A-4F), by etching the conductive layer (etching implicitly disclosed with patterning bit lines 404, ¶ [0063]);
forming a variable resistance pattern (412 patterned over the stack, ¶ [0063]) comprising a first part within the opening and a second part on the stack (Fig. 2), by etching the variable resistance layer (etching implicitly disclosed with patterning 412, ¶ [0063]); and
planarizing the conductive pattern and the variable resistance pattern until the stack is exposed (¶ [0063] discloses the stack subsequently being polished).
Re: Claim 2, Ramaswamy discloses the manufacturing method of claim 1, further comprising forming an isolation structure (isolation materials 214) in a space from which the conductive layer and the variable resistance layer have been etched.
Re: Independent Claim 5, Ramaswamy discloses a method of manufacturing a semiconductor device, comprising:
forming a stack comprising first material layers (conductive material 402, Fig. 4D) and second material layers (insulating material 428, Fig. 4D) that are alternately stacked (Fig. 4D);
forming an opening (via 430) within the stack (Fig. 4A);
forming a memory layer (storage element material 412, Fig. 4F) within the opening and on the stack (Fig. 4F shows 412 inside the via 430 and over the stack);
forming a first conductive layer (bit line 404, Fig. 4F) on the memory layer (Fig. 4F);
forming an isolation structure (solation materials 214) within the memory layer and the first conductive layer (Fig. 2).
planarizing the first conductive layer, the memory layer, and the isolation structure until the stack is exposed (¶ [0063]).
Re: Claim 6, Ramaswamy discloses all the limitations of claim 5 on which this claim depends. Ramaswamy further discloses the memory layer comprises a variable resistance material (¶ [0042]).
Re: Claim 10, Ramaswamy discloses the method of claim 5 and further comprising:
selectively etching the first material layers (402 is etched to form recess 438, Fig. 4A); and
forming a second conductive layer (outer select device material 434, Fig. 4D) in a space (recess 438, Fig. 4A) that has been selectively etched.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ramaswamy (US 20140361239 A1) in view of Pio (US 20140061574 A1).
Re: Claim 3 and Claim 4, Ramaswamy discloses the method of claim 2, and the final product shown in Fig. 2 depicting the over-the-stack layer as the result of the over-the-stack layer in Fig. 4F after masking and etching to form the patterned 204 and 214, in which 204 is the upper conductive portion remaining from the masking of the upper conductive portion 404. Ramaswamy does not explicitly disclose the formation of the trench wherein the insulating layer 214 is subsequently filled in.
Forming a trench to separate the conductive portion over the stack between each memory cell is disclosed in this analogous art of Pio, wherein Pio discloses (Fig. 7C, ¶ [09085]) the formation of individual conductive portions (conductive lines 724) over the stack enabling by the etching/CMP the memory layer (752) and conductive layer (754) over the stack to isolate concentric memory cells from one another. The remaining portions of 752, 754 over the stack are used to form the conductive lines 724. And the etched-away openings between 724 are the trenches.
The forming of the trench over the stack by masking and etching away the exposed portion of the memory layer and the conductive layer formed by blanket deposition to the openings of the memory stack as suggested by Pio would allow the space to fill in the insolation layer to insulate the bit lines of respective memory cells units from one another and to form a planar surface with the bit lines portions ready for subsequent toppings.
Thus, one of ordinary skilled in the art before the filing date of the invention would have applied the bit lines formation of the memory stack by masking and etching away the exposed portion of the upper blanket deposition portion of the conductive layer and the memory layer as taught by Pio to appreciate the formation process of the isolation layer in the final product of Ramaswamy. Filling in the isolation to the trench would result in the bit lines formed from the separated remaining portions of the conductive layer being insulated from one another and providing a planar surface for subsequent design steps.
Ramaswamy’s method as clarified by Pio’s trench making process would result in the masking patterns of the conductive layer acting as the isolated bit lines portions covering the openings of the memory stack and insulated from one another for respective concentric memory units.
Re: Claim 8 and Claim 9, Ramaswamy discloses claim 5 and the final product shown in Fig. 2 depicting the over-the-stack layer as the result of the over-the-stack layer in Fig. 4F after masking and etching to form the patterned 204 and 214, in which 204 is the upper conductive portion remaining from the masking of the upper conductive portion 404. Ramaswamy does not explicitly disclose the formation of the trench wherein the insulating layer 214 is subsequently filled in.
Forming a trench to separate the conductive portion over the stack between each memory cell is disclosed in this analogous art of Pio, wherein Pio discloses (Fig. 7C, ¶ [09085]) the formation of individual conductive portions (conductive lines 724) over the stack enabling by the etching/CMP the memory layer (752) and conductive layer (754) over the stack to isolate concentric memory cells from one another. The remaining portions of 752, 754 over the stack are used to form the conductive lines 724. And the etched-away openings between 724 are the trenches.
The forming of the trench over the stack by masking and etching away the exposed portion of the memory layer and the conductive layer formed by blanket deposition to the openings of the memory stack as suggested by Pio would allow the space to fill in the insolation layer to insulate the bit lines of respective memory cells units from one another and to form a planar surface with the bit lines portions ready for subsequent toppings.
Thus, one of ordinary skilled in the art before the filing date of the invention would have applied the bit lines formation of the memory stack by masking and etching away the exposed portion of the upper blanket deposition portion of the conductive layer and the memory layer as taught by Pio to appreciate the formation process of the isolation layer in the final product of Ramaswamy. Filling in the isolation to the trench would result in the bit lines formed from the separated remaining portions of the conductive layer being insulated from one another and providing a planar surface for subsequent design steps.
Ramaswamy’s method as clarified by Pio’s trench making process would result in the masking patterns of the conductive layer acting as the isolated bit lines portions covering the openings of the memory stack and insulated from one another for respective concentric memory units.
Re: Independent Claim 11 and Claim 12, Ramaswamy discloses a method of manufacturing a semiconductor device, comprising:
forming a stack (alternating insulating materials 428 and conductive materials 402. Fig. 4A);
forming an opening (via 430) within the stack;
forming a memory layer (storage element material 412) within the opening and on the stack (Fig. 4F);
forming a conductive layer (bit lines 404) on the memory layer;
forming conductive patterns (patterns formed on 404 of Fig. 4F as described in [0063]) and
the final product shown in Fig. 2 depicting the over-the-stack layer as the result of the over-the-stack layer in Fig. 4F after masking and etching to form the patterned 204 and 214, in which 204 is the upper conductive portion remaining from the masking of the upper conductive portion 404. Ramaswamy does not explicitly disclose the formation of the trench wherein the insulating layer 214 is subsequently filled in.
Forming a trench to separate the conductive portion over the stack between each memory cell is disclosed in this analogous art of Pio, wherein Pio discloses (Fig. 7C, ¶ [09085]) the formation of individual conductive portions (conductive lines 724) over the stack enabling by the etching/CMP the memory layer (752) and conductive layer (754) over the stack to isolate concentric memory cells from one another. The remaining portions of 752, 754 over the stack are used to form the conductive lines 724. And the etched-away openings between 724 are the trenches.
The forming of the trench over the stack by masking and etching away the exposed portion of the memory layer and the conductive layer formed by blanket deposition to the openings of the memory stack as suggested by Pio would allow the space to fill in the insolation layer to insulate the bit lines of respective memory cells units from one another and to form a planar surface with the bit lines portions ready for subsequent toppings.
Thus, one of ordinary skilled in the art before the filing date of the invention would have applied the bit lines formation of the memory stack by masking and etching away the exposed portion of the upper blanket deposition portion of the conductive layer and the memory layer as taught by Pio to appreciate the formation process of the isolation layer in the final product of Ramaswamy. Filling in the isolation to the trench would result in the bit lines formed from the separated remaining portions of the conductive layer being insulated from one another and providing a planar surface for subsequent design steps.
Ramaswamy’s method as clarified by Pio’s trench making process would result in the masking patterns of the conductive layer acting as the isolated bit lines portions covering the openings of the memory stack and insulated from one another for respective concentric memory units.
Re: Claim 14, Ramaswamy in light of Pio discloses the method of claim 11 and a wiring (WLN, BLN, Fig. 3) is connected to the first part of each of the conductive pattern.
Re: Claim 15, Ramaswamy in light of Pio discloses forming memory patterns (by etching the memory layer (¶ [0063]), each of the memory patterns comprising a first part within the opening (Fig. 2) and a second part that is connected to the first part and disposed over the stack (Fig. 2), wherein the trench separates the memory patterns from each other (212 is separated by the space on which 214 is filled)).
Re: Claim 16, Ramaswamy in light of discloses all the limitations of claim 15 on which this claim depends. Ramaswamy further discloses the isolation structure (214, Fig. 2) is formed between the second parts of an adjacent pair of the conductive patterns and between the second parts of an adjacent pair of the memory patterns.
Re: Claim 17, Ramaswamy in light of Pio discloses all the limitations of claim 11. Ramaswamy further discloses wherein the wiring (the formation of conductive lines out of the remaining portion of the conductive layer per Pio) is connected to the isolation structure and the conductive patterns (Fig. 3).
Re: Claim 18, Ramaswamy in light of Pio discloses the method of claim 17 and the wiring is electrically connected to the conductive patterns and a peripheral circuit (¶ [0002], detailing memory devices connected to internal, semiconductor, integrated circuits).
Claims 7, 12, are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ramaswamy (US 20140361239 A1).
Re: Claim 7, Ramaswamy discloses the method of claim 5 and is silent regarding: the isolation structure comprises a material having greater hardness than the memory layer.
While there is no indication of the hardness of one material over the other, Ramaswamy discloses the memory material and the isolating layer are of different materials, as such their hardnesses are different. Therefore, where the general conditions of a claim are disclosed in the prior art (hardness of materials), it is not inventive to discover the optimum or workable range (hardness differences) by routine experimentation. MPEP 2144.05
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the hardness of the materials according to application. Doing so would strengthen the support of the top layer towards the overall structure of the multilayer memory device.
Re: Claim 12, Ramaswamy discloses method of claim 11 and is silent regarding: the isolation structure has greater hardness than the memory layer.
While there is no indication of the hardness of one material over the other, Ramaswamy discloses the memory material and the isolating layer are of different materials, as such their hardnesses are different. Therefore, where the general conditions of a claim are disclosed in the prior art (hardness of materials), it is not inventive to discover the optimum or workable range (hardness differences) by routine experimentation. MPEP 2144.05
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the hardness of the materials according to application. Doing so would strengthen the support of the top layer towards the overall structure of the multilayer memory device.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Ju (US 20120305877 A1) discloses memory and conductive layers over the stack are separated for each concentric memory cells.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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