DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of species a, figs. 2-4, claims 1-3 and 8-9, in the reply filed on 1/20/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 4-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/20/26.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the following limitation is indefinite:
“wherein a first distance between the first chip and the second chip, and a second distance between the third chip and the fourth chip are less than a third distance between two chips of the plurality of chips that are adjacent to each other in a region closer to the first end side in the first direction than the first chip, and closer to the second end side in the first direction than the fourth chip”.
A diagram of the limitations recited in claim 1 is provided below. Referring to the diagram, the distance between the chips is smaller in the center than the distance between chips at the edge region by the first end side.
However, referring to Applicant’s fig. 4 it appears the distance between the chips is larger in the center than the distance between chips at the edge region by the first end side. Claim 1 appears to recite a distance relationship between the chips that is the opposite of what is shown in Applicant’s fig. 4.
PNG
media_image1.png
372
1408
media_image1.png
Greyscale
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Honda et al., US Publication No. 2017/0317066 A1.
Honda anticipates:
1. A semiconductor device comprising (see fig. 22):
a plurality of chips (Tr),
wherein the plurality of chips comprises a first chip, a second chip (e.g. chips of d53) adjacent to the first chip on a first end side in a first direction (e.g. y-direction), a third chip (e.g. chips of d52) provided closer to the first end side in the first direction than the second chip, and a fourth chip (e.g. chips of d52) adjacent to the third chip on the first end side in the first direction, which are arranged from a second end side to the first end side in the first direction (e.g. y-direction), and
wherein a first distance (d53) between the first chip and the second chip (e.g. chips of d53), and a second distance (d52) between the third chip and the fourth chip (e.g. chips of d52) are less than a third distance (d51) between two chips of the plurality of chips (e.g. chips of d51) that are adjacent to each other in a region closer to the first end side in the first direction than the first chip, and closer to the second end side in the first direction than the fourth chip (e.g. see para. [0051] for the relationship “d51>d52>d53”). See Honda at para. [0001] – [0087], figs. 1-22. Also see the 35 USC 112 rejection above.
2. The semiconductor device according to claim 1,
wherein the plurality of chips further comprises a fifth chip adjacent to the second chip in the first direction between the second chip and the third chip, and
wherein a fourth distance between the second chip and the fifth chip, wherein the fourth distance is equal to or greater than the first distance and equal to or less than the third distance (e.g. See fig. 22 and para. [0051] for the relationship “d51>d52>d53”; also see fig. 21 and para. [0068], for the relationship d41≈d42>d43) Also see the 35 USC 112 rejection above.
8. The semiconductor device according to claim 1, wherein the plurality of chips are arranged above a same base substrate (e.g. 20 in fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Honda, as applied to claim 1 above, and further in view of Bayerer et al., US Publication No. 2016/0056132 A1.
Regarding claim 3:
Honda teaches all the limitations of claim 1 above, but does not expressly teach:
wherein the plurality of chips are arranged on a same conductor.
In an analogous art, Bayerer teaches:
(see fig. 1) wherein the plurality of chips (1) are arranged on a same conductor (72), para. [0051], [0128].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Honda with the teachings of Bayerer to enable the plurality of chips to be connected in series or parallel. See Bayerer at para. [0128].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Honda, as applied to claim 1 above, and further in view of Ogami et al., US Publication No. 2024/0429253 A1.
Regarding claim 9:
Honda teaches all the limitations of claim 1 above, but does not expressly teach:
further comprising: a heat removing member arranged on a lower surface of the base substrate.
In an analogous art, Ogami teaches:
(see fig. 1) further comprising: a heat removing member (6) arranged on a lower surface of a base substrate (33), para. [0068].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Honda with the teachings of Ogami to dissipate heat and improve cooling performance. See Ogami at para. [0068].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michele Fan/
Primary Examiner, Art Unit 2818
22 April 2026
Prosecution Insights