DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election, without traverse, of Group I: claims 1-21 and 29 in the “Response to Election / Restriction Filed - 12/09/2025\”, is acknowledged along with amendment of claims 1 and 18.
This office action considers claims 1-29 pending for prosecution of which claims 22-28 are withdrawn and claims 1-21 and 29 are presented for examination on merits.
Claim Objections
Claim 8 recites the limitation “a depth of a first, first word Line contact” in line 1, and it appears as if Applicant’s representative meant to write ““a depth of a [[first,]] first word Line contact”, Appropriate correction is required. For the prosecution on merit, examiner assumes the phrase as appeared.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.CONCLUSION.—The specification shall conclude with one or more claims particularly
Claims 2 and 13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 2, the instant claim recites limitation in view of claim 1, eherein the claim 2 recites “the plurality of conductive layers” (claim 1, lines 10-11). There is insufficient antecedent basis for this limitation in the claim for “the plurality of conductive layers” in the claim. Appropriate clarification and/or correction are/is required.
Regarding claim 13, the instant claim recites limitation in view of claim 1, eherein the claim 13 recites “the plurality of conductive layers for third word lines” (claim 13, lines ). There is insufficient antecedent basis for this limitation in the claim for “the plurality of conductive layers for third word lines” in the claim. Appropriate clarification and/or correction are/is required. As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of claim 13, it would not be proper for the examiner to reject such a claim on the basis of prior art. See MPEP § 706. 03 and MPEP § 2173.06.II (second) wherein In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.
The prior art made of record form PTO-892 can be used to reject claim 13 once the issues above are resolved.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (1; Fig 1; [0056]) = (element 1; Figure No. 1; Paragraph No. [0036]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation may not be preceded by the inventor tag, wherein the other reference citation will carry inventor tag. These conventions are used throughout this document.
Claim 1-2 and 29 are rejected under 35 U.S.C. 102 (a) (2) as being anticipated by KIM; Junhyoung et al. (US 20230125995 A1) hereinafter Kim;
Regarding claim 1, Kim teaches a memory device (1; Fig 1; [0036]); comprising (see the entire document, figs 9A-9B, 1 to 8 along with other relevant figures, specifically as cited below):
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Kim Figures 9A
a first stack structure (ST_L; Fig 9A-9B; [0144+]; from plate 16 to BP in Fig 9B) comprising a plurality of first interlayer insulating layers (24a/24b; [0145]) and a plurality of conductive layers (27a/27b/27M; [0145]) for first word lines, which are alternately stacked; and
a second stack structure (ST-U; Fig 9A-9B; [0144+]: from BP to top 27B) comprising a plurality of second interlayer insulating layers (24a; [0145]) and a plurality of conductive layers (27a/27b/27M; [0145]) for second word lines, which are alternately stacked;
a first etch stop layer (first adjacent 27a/27b/27M, above BP; Fig 9B; [0084] 27a/27b of material, inter alia, W; etch stop layer is understood from the instant specification [0046, 0048] the first and second etch stop layer 107/115 formed of aluminum oxide (AIO), tungsten (W) or the like; the dependent claim 11 recites the first etch stop layer is a conductive layer’. Examiner note that ., ipsis verbis, such as “etch stop layer” is not required to understand the functionality of “etch stop layer” (See Vas-Cath, 935 F.2d at 1563, 19 USPQ2d at 1116; Martin v. Johnson, 454 F.2d 746, 751, 172 USPQ 391, 395 (CCPA 1972)) disposed between the first stack structure (ST-L) and the second stack structure (ST-U); and
a plurality of first word line contacts (GC such as GCc in Fig 8) extending to the first stack structure (ST_L;) by extending through the second stack structure (ST_U) and extending through the first etch stop layer (first adjacent 27a/27b/27M, above BP).
Regarding claim 2, Kim as applied to the memory device of claim 1, further teaches, wherein each word line of the plurality of first word line contacts, (GCc) is connected to each conductive layer (27a/27b/27M) of the plurality of conductive layers.
Regarding claim 29, Kim teaches a computer system (computing system; Figs 39-41; [0269]), comprising (see the entire document, Figs 39-41 along with figs 9A-9B, 1 to 8 and other relevant figures, specifically, as cited below):
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Kim Figure 39
a processor (1210; Fig 39; [0284]);
a memory system (1100; [0285], operatively coupled (through NAND controller and I/F) to the processor (1210), the memory system storing program instructions for the processor, the memory system (1100) comprising (figs 9A-9B, 1 to 8):
a first stack structure (ST_L; Fig 9A-9B; [0144+]; from plate 16 to BP in Fig 9B) comprising first interlayer insulating layers (24a/24b; [0145]) and conductive layers (27a/27b/27M; [0145]) for first word lines, which are interleaved; and
a second stack structure (ST-U; Fig 9A-9B; [0144+]: from BP to top 27B) comprising second interlayer insulating layers (24a; [0145]) and conductive layers (27a/27b/27M; [0145]) for second word lines, which are interleaved;
a first etch stop layer disposed between the first stack structure and the second stack structure; and
a first etch stop layer (first adjacent 27a/27b/27M, above BP; Fig 9B; [0084] 27a/27b of material, inter alia, W; etch stop layer is understood from the instant specification [0046, 0048] the first and second etch stop layer 107/115 formed of aluminum oxide (AIO), tungsten (W) or the like; the dependent claim 11 recites the first etch stop layer is a conductive layer’. Examiner note that ., ipsis verbis, such as “etch stop layer” is not required to understand the functionality of “etch stop layer” (See Vas-Cath, 935 F.2d at 1563, 19 USPQ2d at 1116; Martin v. Johnson, 454 F.2d 746, 751, 172 USPQ 391, 395 (CCPA 1972)) disposed between the first stack structure (ST-L) and the second stack structure (ST-U); and
first word line contacts (GC such as GCc in Fig 8) extending to the first stack structure (ST_L;) by extending through the second stack structure (ST_U) and extending through the first etch stop layer (first adjacent 27a/27b/27M, above BP)..
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3-11 and14--21 are rejected under 35 U.S.C. 103 as being unpatentable over KIM; Junhyoung et al. (US 20230125995 A1) hereinafter Kim; in view of CHOI; Hoyoung et al. (US 20240090228 A1); hereinafter Choi.
Regarding claim 3, Kim as applied to the memory device of claim 1, but is silent on,(the device) further comprising:
a third stack structure comprising a plurality of third interlayer insulating layers and a plurality of conductive layers for third word lines, which are alternately stacked;
and a second etch stop layer disposed between the second stack structure (ST2) and the third stack structure.
However, in the analogous art, Choi teaches a three-dimensional semiconductor memory device ([0004]), wherein (Figs 6A-6B; [0074]) the stack structure ST includes a first stack structure ST1, a second stack structure ST2, and a third stack structure ST3 that are sequentially stacked. The first stack structure ST1 may include first gate electrodes EL1 and first interlayer dielectric layers ILD1 that are alternately stacked in the third direction D3 on the second substrate 100. The second stack structure ST2 may include second gate electrodes EL2 and second interlayer dielectric layers ILD2 that are alternately stacked in the third direction D3 on the first stack structure ST1. The third stack structure ST3 may include third gate electrodes EL3 and third interlayer dielectric layers ILD3 that are alternately stacked in the third direction D3 on the second stack structure ST2.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chois’s configuration of ST3 over Kim’s ST_U duplicating similar patterns of etch stop layer (bottom gate electrode, conducting layers and ILD layers, and VCS layer, thereafter the combination of (Kim and Choi) device comprises a third stack structure (ST3) comprising a plurality of third interlayer insulating layers (24a in view of Choi ILD3) and a plurality of conductive layers (27a/27b/27M in view of Choi EL3) for third word lines, which are alternately stacked;
and a second etch stop layer (bottom 27s/27b/27M in view of Choi bottom ILD3) disposed between the second stack structure (ST-U) and the third stack structure (Choi ST3), since this inclusion, at least, increase the capacity of the memory device and as per MPEP § 2144.4.VI.B, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding claim 4, the combination of (Kim and Choi) as applied to the memory device of claim 3, further teaches, (the device) comprising a plurality of second word line contacts extending to the inside of the second stack structure (ST_U) by extending through the third stack structure (Choi ST3) and extending through the second etch stop layer (bottom 27s/27b/27M in view of Choi bottom ILD3).
Regarding claim 5, the combination of (Kim and Choi) as applied to the memory device of claim , further teaches, wherein each word line of the plurality of second word line contacts (GCc) is connected to each conductive layer of the plurality of conductive layers for second word lines (27a/27b/27M).
Regarding claim 6, the combination of (Kim and Choi) as applied to the memory device of claim 4, further teaches, (the device) further comprising a plurality of third word line contacts (duplicated GCc) extending to the third stack structure (Choi ST3) and which are connected to each of the plurality of conductive layers (27s/27b/27M in view of Choi ILD3) for third word lines.
Regarding claim 7, the combination of (Kim and Choi) as applied to the memory device of claim 6, further teaches, wherein depths of the first word line contacts (GCc in ST_L), the second word line contacts (GCc in ST_U), and the third word line contacts (duplicated GCc in Choi ST3) are different (obvious from (\Fig 9A and Choi Fig 6A) .
Regarding claim 8, the combination of (Kim and Choi) as applied to the memory device of claim 6, further teaches, wherein a depth of a [[first,]] first word line contact (GCc in ST_L) located proximate to the center of the plurality of first word line contacts, exceeds the depth of a second (GCc in ST_U), first word line contact located away from the center of the plurality of first word line contacts, and
wherein depths of first word line contacts decrease as separation distances of the first word line contacts from the center of the plurality of first word line contacts increases (obvious from Fig 9A and Choi Fig 6A).
Regarding claim 9, the combination of (Kim and Choi) as applied to the memory device of claim 4, further teaches, wherein a depth of second word line contacts increases, as separation distances of second word line contacts from the center of the plurality of second word line contacts decreases, and
wherein depths of the second word line contacts decrease as separation distances of second word line contacts from the center of the plurality of second word line contacts increase (obvious from Fig 9A and Choi Fig 6A).
Regarding claim 10, the combination of (Kim and Choi) as applied to the memory device of claim 6, further teaches, wherein a depth of a third word line contact increases as a separation distance between the third word line contact and the center of the plurality of third word line contacts decreases (obvious from Fig 9A and Choi Fig 6A).
Regarding claim 11, the combination of (Kim and Choi) as applied to the memory device of claim 1, wherein the first etch stop layer is a conductive layer (first adjacent 27a/27b/27M, above BP; Fig 9B; [0084] 27a/27b of material, inter alia, W, which is conductive) for word lines (obvious from Fig 9A and Choi 6A).
Regarding claim 14, Kim teaches a memory device (1; Fig 1; [0036]); comprising (see the entire document, figs 9A-9B, 1 to 8 along with other relevant figures, specifically as cited below):
a first stack structure (ST_L; Fig 9A-9B; [0144+]; from plate 16 to BP in Fig 9B) including a plurality of first interlayer insulating layers (24a/24b; [0145]) and a plurality of conductive layers (27a/27b/27M; [0145]) for first word lines, which are alternately stacked;
a first etch stop layer (first adjacent 27a/27b/27M, above BP; Fig 9B; [0084] 27a/27b of material, inter alia, W; etch stop layer is understood from the instant specification [0046, 0048] the first and second etch stop layer 107/115 formed of aluminum oxide (AIO), tungsten (W) or the like; the dependent claim 11 recites the first etch stop layer is a conductive layer’. Examiner note that ., ipsis verbis, such as “etch stop layer” is not required to understand the functionality of “etch stop layer” (See Vas-Cath, 935 F.2d at 1563, 19 USPQ2d at 1116; Martin v. Johnson, 454 F.2d 746, 751, 172 USPQ 391, 395 (CCPA 1972)) formed on the first stack structure (ST-L);
a second stack structure (ST-U; Fig 9A-9B; [0144+]: from BP to top 27B) formed on the first etch stop layer (first adjacent 27a/27b/27M, above BP), the second stack structure including a plurality of second interlayer insulating layers (24a; [0145]) and a plurality of conductive layers (27a/27b/27M; [0145]) for second word lines, which are alternately stacked;
But, Kim does not expressly disclose:
“a second etch stop layer formed on the second stack structure;
a third stack structure formed on the second etch stop layer, the third stack structure including a plurality of third interlayer insulating layers and a plurality of conductive layers for third word lines, which are alternately stacked; and
a plurality of first word line contacts extending to the first stack structure by extending through: the third stack structure; the second etch stop layer; the second stack structure; and the first etch stop layer”
However, in the analogous art, Choi teaches a three-dimensional semiconductor memory device ([0004]), wherein (Figs 6A-6B; [0074]) the stack structure ST includes a first stack structure ST1, a second stack structure ST2, and a third stack structure ST3 that are sequentially stacked. The first stack structure ST1 may include first gate electrodes EL1 and first interlayer dielectric layers ILD1 that are alternately stacked in the third direction D3 on the second substrate 100. The second stack structure ST2 may include second gate electrodes EL2 and second interlayer dielectric layers ILD2 that are alternately stacked in the third direction D3 on the first stack structure ST1. The third stack structure ST3 may include third gate electrodes EL3 and third interlayer dielectric layers ILD3 that are alternately stacked in the third direction D3 on the second stack structure ST2.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chois’s configuration of ST3 over Kim’s ST_U duplicating similar patterns of etch stop layer (bottom gate electrode, conducting layers and ILD layers, and VCS layer, thereafter the combination of (Kim and Choi) device comprises a second etch stop layer (bottom 27s/27b/27M in view of Choi bottom ILD3); a third stack structure (ST3) formed on the second etch stop layer (bottom 27s/27b/27M in view of Choi bottom ILD3), the third stack structure including a plurality of third interlayer insulating layers (24a in view of Choi ILD3) and a plurality of conductive layers (27a/27b/27M in view of Choi EL3) for third word lines, which are alternately stacked, since this inclusion, at least, increase the capacity of the memory device and as per MPEP § 2144.4.VI.B, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); and
the combination of (Kim and Choi) device further comprises a plurality of first word line contacts (GC such as GCc in Fig 8) extending to the first stack structure (ST_L) by extending through: the third stack (Choi ST3) structure; the second etch stop layer (bottom 27s/27b/27M in view of Choi bottom ILD3); the second stack structure (ST-U) ; and the first etch stop layer (first adjacent 27a/27b/27M, above BP)).
Regarding claim 15, the combination of (Kim and Choi) as applied to the memory device of claim 14, further teaches, (the device) further comprising a plurality of second word line contacts (GCc) extending to the second stack structure (ST-U) by extending through the third stack structure (Choi ST3) and the second etch stop layer (bottom 27s/27b/27M in view of Choi bottom ILD3).
Regarding claim 16, the combination of (Kim and Choi) as applied to the memory device of claim 15, further teaches, (the device) further comprising a plurality of third word line contacts (duplicated GCc) extending to the third stack structure (Choi ST3).
Regarding claim 17, the combination of (Kim and Choi) as applied to the memory device of claim 14, further teaches, wherein each of the first etch stop layer and the second etch stop layer is a conductive layer (first adjacent 27a/27b/27M, above BP; Fig 9B; [0084] 27a/27b, Choi ELD of material, inter alia, W, which is conductive).
Regarding claim 18, the combination of (Kim and Choi) as applied to the memory device of claim 14, further teaches, wherein the plurality of conductive layers (GCc in ST_L) for first word lines, the plurality of conductive layers for second word lines (GCc in ST_U), and the plurality of conductive layers (duplicated GCc in Choi ST3) for third word lines are substantially horizontal and have substantially equal lengths (obvious from Fig 9A and Cho Fig 6A).
Regarding claim 19, the combination of (Kim and Choi) as applied to the memory device of claim 14, further teaches, wherein a depth of a first word line contact (GCc in ST_L) increases as a separation distance between the first word line contact and the center of the plurality of first word line contacts decreases (obvious from Fig 9A and Choi Fig 6A)..
Regarding claim 20, the combination of (Kim and Choi) as applied to the memory device of claim 15, further teaches, wherein a depth of a second word line contact (GCc in ST_U) increases as a separation distance between the second word line contact and the center of the plurality of second word line contacts decreases (obvious from Fig 9A and Choi Fig 6A)..
Regarding claim 21, the combination of (Kim and Choi) as applied to the memory device of claim 1, further teaches, wherein a depth of a third word line (duplicated GCc in Choi ST3) increases as a separation distance between the third word line contact and the center of the plurality of third word line contacts decreases (obvious from Fig 9A and Choi Fig 6A).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over KIM; Junhyoung et al. (US 20230125995 A1) hereinafter Kim; in view of CHOI; Hoyoung et al. (US 20240090228 A1); hereinafter Choi, in further view of SUN; Zhongwang et al. (US 20210287991 A1); hereinafter Sun.
Regarding claim 12, the combination of (Kim and Choi) as applied to the memory device of claim 6, does not expressly disclose (the device) further comprising a barrier layer extending in a vertical direction along a sidewall of each word line contact (GGc).
However, in the analogous art, Sun teaches CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY (Title), wherein (fig 4,15; [0107-0108]) the contact fill 1584 also include a liner 1587 of an insulator, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, amorphous carbon, and/or a combination thereof.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Sun’s line as Kim’s barrier layer extending in a vertical direction along a sidewall of each word line contact (GGc), since this inclusion will prevent diffusion metallic ion into ILD.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
June 8, 2026
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