Prosecution Insights
Last updated: April 19, 2026
Application No. 18/459,230

INTEGRATED CIRCUIT WITH INDUCTOR IN MAGNETIC PACKAGE

Non-Final OA §103
Filed
Aug 31, 2023
Examiner
LEE, EUGENE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
87%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
728 granted / 891 resolved
+13.7% vs TC avg
Minimal +5% lift
Without
With
+4.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
930
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
41.1%
+1.1% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
24.5%
-15.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 891 resolved cases

Office Action

§103
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Group I (claims 1-15) in the reply filed on 12/29/25 is acknowledged. Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/25. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 thru 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. US 2021/0343662 A1 in view of Kawabata US 2018/0158782 A1. Sato discloses (see, for example, FIG. 9) a package integrated circuit (IC) comprising a package substrate 802, electronic device 804, insulation material 834, and inductor 810/812. Sato does not clearly disclose metal interconnects coupled between the electronic device and the package substrate. However, Kawabata discloses (see, for example, FIG. 3) a package integrated circuit 11C comprising metal interconnects 24 packaged between the electronic device 31, and the package substrate 20. It would have been obvious to one of ordinary skill in the art to have metal interconnects coupled between the electronic device and the package substrate in order to improve the connection between the electronic device and package substrate, and also provide further connections outside of the substrate to make more robust electrical devices according to the preferences of the user. Sato does not clearly disclose magnetic material on the insulating material and encapsulating the inductor, in which the magnetic material is different from the insulation material. However, Kawabata discloses (see, for example, FIG. 3) a package integrated circuit 11C comprising a magnetic material 50 on an insulating material 40. It would have been obvious to one of ordinary skill in the art to include magnetic material on the insulating material and encapsulating the inductor, in which the magnetic material is different from the insulation material in order to improve the effective permeability and reduce noise within the package integrated circuit. Regarding claim 2, Sato does not clearly disclose the insulation material includes non-electrically conductive particles and a first epoxy resin in which the non-electrically conductive particles are suspended; however, Kawabata discloses (see, for example, paragraph [0042] and [0045]) an insulation material 40 including non-magnetic filler. It would have been obvious to one of ordinary skill in the art to have the insulation material includes non-electrically conductive particles and a first epoxy resin in which the non-electrically conductive particles being suspended in order to enhance insulating performance and withstand voltage performance of the insulating material. Regarding claims 3, and 12, see, for example, paragraph [0046] wherein Kawabata discloses magnetic fillers dispersed in a thermosetting resin material. Regarding claims 4, and 13, see, for example, paragraph [0048] wherein Kawabata discloses multiple metals formed in the magnetic material, which lowers the breakdown voltage in the magnetic material Regarding claim 5, see, for example, FIG. 9 wherein Sato discloses a semiconductor die 804. Regarding claim 6, see, for example, paragraph [0034] wherein Sato discloses a capacitor. Regarding claims 7, and 14, see, for example, FIG. 9 wherein Sato discloses the inductor has a coil portion 810/812, first stilt 828, and second stilt 818, the first and second stilts are coupled to the package substrate 802 at opposing sides of the electronic device 804. Regarding claim 8, see, for example, FIG. 9 wherein Sato discloses first metal post 830 and second metal post 822. Regarding claim 9, see, for example, FIG. 9 wherein Sato discloses first metal pad 808, and second metal pad 806, and FIG. 3 wherein Kawabata discloses third metal pads 23. Regarding claims 10, and 15, see, for example, FIG. 9 wherein Sato discloses the insulation material 834 covers at least a part of the package substrate 802. Regarding claim 11, see the rejection for claims 1, and 2 above. Further, in paragraph [0034], Sato discloses the package substrate includes lead frame. INFORMATION ON HOW TO CONTACT THE USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Eugene Lee January 15, 2026 /EUGENE LEE/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Aug 31, 2023
Application Filed
Jan 16, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
87%
With Interview (+4.9%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 891 resolved cases by this examiner. Grant probability derived from career allow rate.

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