DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 06/18/2026.
Applicant’s amendments filed 06/18/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1, 5-6, and 9-10; the cancellation of claims 11-20; and the addition of new claims 21-26.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21 and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 21 (claim 24) recites limitation “the block insulating films”. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the block insulating films” relate back to “a pair of block insulating films” recited in lines 5-6 of claim 1 or to set forth additional block insulating films.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,032,935 to Higuchi et al. (hereinafter Higuchi) in view of Xiao (US 2020/0312868).
Claims 1-8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 10,032,935 to Higuchi et al. (hereinafter Higuchi).
With respect to claim 1, Higuchi discloses a semiconductor device (e.g., NAND-type flash memory, see the annotated Fig. 5 below) (Higuchi, Figs. 1-5, Col. 1, lines 15-17; Col. 2, lines 1-67; Cols. 3-7), comprising:
a film stack (12) (Higuchi, Figs. 4-5, Col. 3, lines 38-55) including first films (e.g., 14A/14B and 51, W/TiN and alumina) and first insulating films (e.g., 15, SiO2) alternatingly stacked in a first direction (e.g., the Z-direction), the first films (e.g., 14A/14B and 51, W/TiN and alumina) each including an electrode layer (14A/14B) and a second insulating film (51, alumina) disposed on an upper face, a lower face, and a side face of the electrode layer (14A/14B);
a semiconductor layer (20, a channel of the memory cell MC) (Higuchi, Figs. 4-5, Col. 4, lines 33-48) extending in the first direction (e.g., the Z-direction);
a charge accumulating layer (40) (Higuchi, Figs. 4-5, Col. 4, lines 33-36; Col. 5, lines 1-67) between the semiconductor layer (20) and the film stack (12) in a second direction (e.g., X-direction) perpendicular to the first direction (e.g., Z-direction), the charge accumulating layer (40) having first portions (e.g., a thicker portion 40B) (Higuchi, Figs. 4-5, Col. 5, lines 1-26) between the first films (14/51) and the semiconductor layer (20) in the second direction (e.g., X-direction) and second portions (e.g., a thin portion 40A) between the first insulating films (15) and the semiconductor layer (20) in the second direction (e.g., X-direction), the first portions (40B) each having a first thickness in the second direction, and the second portions each having a second thickness in the second direction, the second thickness (e.g., the thin portion 40A is thinner than the first portion 40B) being less than the first thickness, wherein
at least one of the first portions (40B) has a first width (e.g., a width of the charge-storing part 40B) (Higuchi, Figs. 4-5, Col. 5, lines 30-50) in the first direction (e.g., Z-direction), and
at least one of the first films (14/51) (Higuchi, Figs. 4-5, Col. 5, lines 30-50) has a second width in the first direction (e.g., Z-direction), the second width being less than the first width.
Further, Higuchi does not specifically disclose that the first insulating films each including a third insulating film between a pair of block insulating films in the first direction.
However, Xiao discloses forming a semiconductor device (Xiao, Fig. 2B, ¶0005, ¶0006, ¶0035, ¶0042, ¶0050) comprising a gate-to-gate dielectric layer (206) (Xiao, Fig. 2B, ¶0042, ¶0050) between gate conductive layers (202) and including a third insulating film (e.g., a silicon oxynitride layer 208) between a pair of block insulating films (e.g., two silicon oxide layers 210) in the first direction (e.g., a vertical direction), to improve barrier performance and to reduce gate-to gate coupling and leakage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Higuchi by forming the first insulating films as a gate-to-gate dielectric layer including a silicon oxynitride layer as a third insulating film between a pair of block insulating films including silicon oxide layers as taught by Xiao to have the semiconductor device, wherein the first insulating films each including a third insulating film between a pair of block insulating films in the first direction, in order to improve barrier performance and to reduce gate-to gate coupling and leakage (Xiao, ¶0005, ¶0035, ¶0042, ¶0050).
Regarding claim 2, Higuchi in view of Xiao discloses the semiconductor device according to claim 1. Further, Higuchi discloses the semiconductor device, wherein the first insulating films (e.g., 15, SiO2) (Higuchi, Figs. 4-5, Col. 3, lines 49-51) comprise silicon and oxygen.
Regarding claim 3, Higuchi in view of Xiao discloses the semiconductor device according to claim 1. Further, Higuchi discloses the semiconductor device, wherein the second insulating film (51, alumina (Al2O3)) (Higuchi, Figs. 4-5, Col. 3, lines 54-55) comprises a metal element (e.g., aluminum (Al)).
Regarding claim 4, Higuchi in view of Xiao discloses the semiconductor device according to claim 3. Further, Higuchi discloses the semiconductor device, wherein the metal element is aluminum (Al) (Higuchi, Figs. 4-5, Col. 3, lines 54-55).
Regarding claim 5, Higuchi in view of Xiao discloses the semiconductor device according to claim 1. Further, Higuchi discloses the semiconductor device, further comprising: fourth insulating films (e.g., blocking insulation film 50) (Higuchi, Figs. 4-5, Col. 4, lines 33-36; Col. 7, lines 11-23) between each first portion (40B) and the first films (14/51) in the second direction (e.g., the X-direction).
Regarding claim 6, Higuchi in view of Xiao discloses the semiconductor device according to claim 1. Further, Higuchi discloses the semiconductor device, further comprising: a fifth insulating film (e.g., tunnel insulation film 30) (Higuchi, Figs. 4-5, Col. 4, lines 33-36; lines 62-67) between the semiconductor layer (20) and the film stack (12) in the second direction (e.g., the X-direction), wherein the fifth insulating film (30) is a continuous film along a length of the semiconductor layer (20) in the first direction (e.g., the Z-direction).
Regarding claim 7, Higuchi in view of Xiao discloses the semiconductor device according to claim 1. Further, Higuchi discloses the semiconductor device, wherein the charge accumulating layer (40) comprises silicon and nitrogen (e.g., silicon nitride (SiN) and silicon oxynitride (SiON)) (Higuchi, Figs. 4-5, Col. 6, lines 1-8).
Regarding claim 8, Higuchi in view of Xiao discloses the semiconductor device according to claim 7. Further, Higuchi discloses the semiconductor device, wherein the charge accumulating layer (40) further comprises oxygen (e.g., silicon oxynitride (SiON) including oxygen) (Higuchi, Figs. 4-5, Col. 6, lines 1-5).
Regarding claim 10, Higuchi in view of Xiao discloses the semiconductor device according to claim 7. Further, Higuchi discloses the semiconductor device, wherein the charge accumulating layer (40) (Higuchi, Figs. 4-5, Col. 4, lines 33-36; Col. 6, lines 6-58) is continuous along a length of the semiconductor layer (20) in the first direction (e.g., the Z-direction).
Regarding claims 21 and 22, Higuchi in view of Xiao discloses the semiconductor device according to claim 5. Further, Higuchi does not specifically disclose that the fourth insulating films and the block insulating films are a same material (as claimed in claim 21); further comprising: fifth insulating films, each fifth insulating film being between one of the third insulating films and one second portion of the charge accumulating layer in the second direction and between different first portions of the charge accumulating layer in the first direction (as claimed in claim 22).
However, Higuchi discloses the semiconductor device, wherein the fourth insulating films (e.g., blocking insulation film 50) (Higuchi, Figs. 4-5, Col. 4, lines 33-36; Col. 7, lines 11-23) includes silicon oxide (SiO2). Further, Xiao teaches that the block insulating films (e.g., two silicon oxide layers 210) includes silicon oxide (SiO2) (Xiao, Fig. 2B, ¶0042), to improve barrier performance and to reduce gate-to gate coupling and leakage.
Further, Higuchi discloses the semiconductor device, further comprising: fifth insulating films, each fifth insulating film (e.g., a portion of insulating film 50 directly adjacent to the second portions 40A of the charge accumulating layer) (Higuchi, Figs. 4-5, Col. 5, lines 1-26) being between one of the third insulating films (e.g., SiON layer between two silicon oxide layers of the gate-to gate dielectric film of Higuchi/Xiao) and one second portion (40A) of the charge accumulating layer in the second direction and between different first portions (40B) of the charge accumulating layer in the first direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Higuchi/Xiao by forming the first insulating films as a gate-to-gate dielectric layer including a silicon oxynitride layer as a third insulating film between a pair of block insulating films including silicon oxide layers as taught by Xiao, and forming a fifth insulating film directly adjacent to the second portions of the charge accumulating layer and the third insulating film of Higuchi/Xiao to have the semiconductor device, wherein the fourth insulating films and the block insulating films are a same material (as claimed in claim 21); further comprising: fifth insulating films, each fifth insulating film being between one of the third insulating films and one second portion of the charge accumulating layer in the second direction and between different first portions of the charge accumulating layer in the first direction (as claimed in claim 22), in order to improve barrier performance and to reduce gate-to gate coupling and leakage, and to provide memory device with improved charge-holding characteristics (Xiao, ¶0005, ¶0035, ¶0042, ¶0050; Higuchi, Col. 1, lines 21-22; Col. 10, lines 17-25).
Regarding claims 23-24, Higuchi in view of Xiao discloses the semiconductor device according to claim 22. Further, Higuchi does not specifically disclose that each of the fifth insulating films directly contacts both of the different first portions of the charge accumulating layer in the first direction (as claimed in claim 23); wherein an interface between the fifth insulation films and the third insulating films is closer to the semiconductor layer in the second direction than is an interface between the block insulation films and the charge accumulating layer (as claimed in claim 24).
However, Higuchi discloses the semiconductor device, wherein each of the fifth insulating films (e.g., a portion of insulating film 50 directly adjacent to the second thin portions 40A of the charge accumulating layer) (Higuchi, Figs. 4-5, Col. 5, lines 1-26) directly contacts both of the different first portions (e.g., thick portions 40B of the charge accumulating layer) of the charge accumulating layer in the first direction, wherein an interface between the fifth insulation films (e.g., 50, directly adjacent to the second thin portions 40A) and the third insulating films (e.g., SiON layer between two silicon oxide layers of the gate-to gate dielectric film of Higuchi/Xiao) is closer to the semiconductor layer (20) in the second direction than is an interface between the block insulation films (e.g., portion of insulating film 50 including blocking silicon oxide layer of Higuchi/Xiao) and the charge accumulating layer (e.g., thick portion 40B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Higuchi/Xiao by forming the first insulating films as a gate-to-gate dielectric layer including a silicon oxynitride layer as a third insulating film between a pair of block insulating films including silicon oxide layers as taught by Xiao, and forming fifth insulating films directly adjacent to the second portions of the charge accumulating layer and the third insulating film of Higuchi/Xiao to have the semiconductor device, wherein each of the fifth insulating films directly contacts both of the different first portions of the charge accumulating layer in the first direction (as claimed in claim 23); wherein an interface between the fifth insulation films and the third insulating films is closer to the semiconductor layer in the second direction than is an interface between the block insulation films and the charge accumulating layer (as claimed in claim 24), in order to improve barrier performance and to reduce gate-to gate coupling and leakage, and to provide memory device with improved charge-holding characteristics (Xiao, ¶0005, ¶0035, ¶0042, ¶0050; Higuchi, Col. 1, lines 21-22; Col. 10, lines 17-25).
Regarding claim 25, Higuchi in view of Xiao discloses the semiconductor device according to claim 22. Further, Higuchi discloses the semiconductor device, further comprising: a sixth insulating film (e.g., tunnel insulation film 30) (Higuchi, Figs. 4-5, Col. 4, lines 33-36; lines 62-67) between the between the semiconductor layer (20) and the film stack in the second direction, wherein the sixth insulating film is a continuous.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,032,935 to Higuchi in view of Xiao (US 2020/0312868) as applied to claim 8, and further in view of Kang et al. (US 2018/0166458, hereinafter Kang).
Regarding claim 9, Higuchi in view of Xiao discloses the semiconductor device according to claim 8. Further, Higuchi does not specifically disclose the semiconductor device, wherein a number of oxygen atoms in the charge accumulating layer is 12% or less of a total number of silicon atoms, nitrogen atoms, and oxygen atoms in the charge accumulating layer.
However, Kang teaches forming a non-volatile memory cell (Kang, Fig. 5a, ¶0008, ¶0046-¶0054) comprising a charge storage layer (548b) (Kang, Fig. 5a, ¶0052) comprising a silicon oxynitride (SiON) including silicon, oxygen, and nitrogen in various stoichiometries to provide desired trap density and to located a centroid of the trapped charge within a top of the nitride layer to improve charge retention. Specifically, the charge storage layer comprises an oxygen-rich SiON layer with a concentration of oxygen from about 15 % to about 40 %, and an oxygen-lean SiON layer with a concentration of oxygen less than about 5 %.
Thus, Kang recognizes that a concentration of oxygen of the charge storage layer impacts trap density and charge retention. Thus, a concentration of oxygen of the charge storage layer is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a concentration of oxygen of the charge storage layer as Kang has identified a concentration of oxygen of the charge storage layer as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific concentration of oxygen of the charge storage layer, wherein a number of oxygen atoms in the charge accumulating layer is 12% or less of a total number of silicon atoms, nitrogen atoms, and oxygen atoms in the charge accumulating layer, in order to provide desired trap density and to improve charge retention as taught by Kang (¶0052) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Higuchi/Xiao by optimizing a concentration of oxygen of charge accumulating layer as taught by Kang to have the semiconductor device, wherein a number of oxygen atoms in the charge accumulating layer is 12% or less of a total number of silicon atoms, nitrogen atoms, and oxygen atoms in the charge accumulating layer, in order to provide improved non-volatile memory cell including a charge accumulating layer in stoichiometry to have a desired trap density and to improve charge retention (Kang, ¶0002, ¶0008, ¶0052).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,032,935 to Higuchi in view of Xiao (US 2020/0312868) as applied to claim 8, and further in view of Pang et al. (US 2016/0093636, hereinafter Pang) and Kang (US 2018/0166458).
Regarding claim 9, Higuchi in view of Xiao discloses the semiconductor device according to claim 8. Further, Higuchi does not specifically disclose the semiconductor device, wherein a number of oxygen atoms in the charge accumulating layer is 12% or less of a total number of silicon atoms, nitrogen atoms, and oxygen atoms in the charge accumulating layer.
However, Pang teaches forming a charge-trapping layer arranged vertically in the tree-dimensional (3D) stacked memory structure (Pang, Figs. 7-8, ¶0033-¶0037, ¶0100-¶0146), wherein the charge-trapping layer of SiON comprises Si-rich SiON portions adjacent to the conductive layers of the stack and not Si-rich for the dielectric-adjacent portions of the stack (Pang, Figs. 7-8, ¶0122). Different atomic percent of silicon (Si) and oxygen (O) in the SiON layer controls the refractive index (RI) of the charge-trapping layer, wherein the RI increases (Pang, Figs. 7-8, ¶0136) in proportion to the amount of Si and the amount of oxygen decreases in the Si-rich SiON portions, such that the portions of the charge-trapping layer which are adjacent to the word line layers have a refractive index which is higher than a refractive index of the portions of the charge-trapping layer which are adjacent to the dielectric layers. The charge-trapping region with a higher refractive index guarantees the proper program, erase and endurance characteristics of the memory cells (Pang, Figs. 7-8, ¶0100); and the charge-trapping region with a lower refractive index has a lower trap density, thus reducing the possibility of trap-assisted tunneling and suppressing the lateral charge migration. Moreover, the larger the difference between the higher and lower refractive indexes, the more effective the isolation between the memory cells so that better data retention is achieved.
Further, Kang teaches forming a non-volatile memory cell (Kang, Fig. 5a, ¶0008, ¶0046-¶0054) comprising a charge storage layer (548b) (Kang, Fig. 5a, ¶0052) comprising a silicon oxynitride (SiON) including silicon, oxygen, and nitrogen in various stoichiometries to provide desired trap density and to located a centroid of the trapped charge within a top of the nitride layer to improve charge retention. Specifically, the charge storage layer comprises an oxygen-rich SiON layer with a concentration of oxygen from about 15 % to about 40 %, and an oxygen-lean SiON layer with a concentration of oxygen less than about 5 %.
Thus, Pang recognizes that a concentration of oxygen of the charge storage layer impacts lateral charge migration and charge retention. Further, Kang recognizes that a concentration of oxygen of the charge storage layer impacts trap density and charge retention. Thus, a concentration of oxygen of the charge storage layer is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a concentration of oxygen of the charge storage layer as Pang and Kang have identified a concentration of oxygen of the charge storage layer as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific concentration of oxygen of the charge storage layer, wherein a number of oxygen atoms in the charge accumulating layer is 12% or less of a total number of silicon atoms, nitrogen atoms, and oxygen atoms in the charge accumulating layer, in order to provide desired trap density and to improve charge retention as taught by Kang (¶0052) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Higuchi/Xiao by optimizing a concentration of oxygen of the Si-rich SiON portions of the charge-trapping layer adjacent to the word line layers and a concentration of oxygen of the not-Si-rich SiON portions of the charge-trapping layer adjacent to the dielectric layers as taught by Pang, wherein the concentration of oxygen of the Si-rich SiON portions is less than 5 % as taught by Kang to have the semiconductor device, wherein a number of oxygen atoms in the charge accumulating layer is 12% or less of a total number of silicon atoms, nitrogen atoms, and oxygen atoms in the charge accumulating layer, in order to suppress the lateral charge migration and improve data retention; and to provide improved non-volatile memory cell including charge accumulating layer stoichiometries to have a desired trap density and to improve charge retention (Pang, ¶0033-¶0037, ¶0100, ¶0136; Kang, ¶0002, ¶0008, ¶0052).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,032,935 to Higuchi in view of Xiao (US 2020/0312868) as applied to claim 25, and further in view of Nishikawa et al. (US 2020/0168623, hereinafter Nishikawa).
Regarding claim 26, Higuchi in view of Xiao discloses the semiconductor device according to claim 25. Further, Higuchi does not specifically disclose the semiconductor device, wherein a maximum dimension of the fifth insulation films along the second direction is 2 nm, the second thickness of the second portions is 2 nm, and a maximum dimension of the sixth insulation film along the second direction is 5 nm, and a maximum dimension of the semiconductor layer along the second direction is 5 nm.
However, Nishikawa teaches forming a three-dimensional semiconductor device (Nishikawwa, Fig. 9E, ¶0001, ¶0003-¶0004, ¶0035-¶0089), wherein a maximum dimension of the fifth insulation films (52, tubular blocking dielectric) (Nishikawwa, Fig. 9E, ¶0074) along the second direction is between 2 nm and 6 nm, the second thickness of the second portions of the charge storage layer (54) (Nishikawwa, Fig. 9E, ¶0076) is between 2 nm and 20 nm, and a maximum dimension of the sixth insulation film (e.g., a continuous tunneling layer 56L) (Nishikawwa, Fig. 9E, ¶0079) along the second direction is between 2 nm and 20 nm, and a maximum dimension of the semiconductor layer (601L/602, each has a thickness between 2 nm and 10 nm) (Nishikawwa, Fig. 9E, ¶0080, ¶0085-¶0086) along the second direction is between 4 nm and 20 nm, to provide improved NAND memory device comprising a vertical semiconductor channel on the memory films with a macroscopic retention time (Nishikawwa, ¶0089).
The claimed dimensions/thicknesses are within ranges disclosed by the prior art of Nishikawa. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Higuchi/Xiao by forming a three-dimensional NAND string device comprising conventional dimensions/thicknesses of the channel layer and memory layers as taught by Nishikawa to have the semiconductor device, wherein a maximum dimension of the fifth insulation films along the second direction is 2 nm, the second thickness of the second portions is 2 nm, and a maximum dimension of the sixth insulation film along the second direction is 5 nm, and a maximum dimension of the semiconductor layer along the second direction is 5 nm, in order to provide improved NAND memory device comprising a vertical semiconductor channel on the memory films with a macroscopic retention time (Nishikawwa, ¶0001, ¶0003-¶0004, ¶0076-¶0077, ¶0080, ¶0085-¶0086, ¶0089).
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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