DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 05/08/2026 is acknowledged. Claims 15-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim, and election was made without traverse in the amendment filed on 05/08/2026.
Therefore, claims 1-14 and 19-20 have been fully considered in examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites “a plurality of gate electrode pillars, each extending in a first direction and spaced from each other in second and third directions perpendicular to the first direction.” It is unclear whether each pillar must be spaced from every other pillar in both the second and third directions, or whether the pillars are merely arranged in rows and columns along those directions. It is also unclear whether the second and third directions are mutually perpendicular, merely different, or coincident.
Claims 19-20 are also rejected being dependent on rejected claim 19.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu (US 20220285506 A1), and further in view of Hopkins (US 10170639 B2).
Regarding claim 1, Zhu teaches a semiconductor memory device (Zhu, Para [0002], a NOR-type storage device), comprising:
a first gate electrode layer extending in a first direction (Zhu, Para [0053]–[0057]; FIG. 6, gate stack extending vertically, gate conductor layer);
a first semiconductor layer surrounding the first gate electrode layer (Zhu, Para [0056], [0101]; FIG. 6, active region surrounding the gate stack; first channel region);
a second semiconductor layer in the first direction from the first semiconductor layer and surrounding the first gate electrode layer (Zhu, Para [0056], [0058], second channel region, vertically spaced, surrounding the gate stack);
a first electrode layer surrounding the first gate electrode layer and in contact with the first semiconductor layer (Zhu, Para [0056]–[0058]; FIG. 6, first source/drain defining layer surrounding the gate stack, contacting the first channel region);
a second electrode layer in the first direction from the first electrode layer, the second electrode layer surrounding the first gate electrode layer and in contact with the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being between the first electrode layer and the second electrode layer (Zhu, Para [0058], [0024], second source/drain defining layer surrounding the gate stack, contacting and shared by both channel regions; first channel region between the first and second source/drain regions);
a third electrode layer in the first direction from the second electrode layer, the third electrode layer surrounding the first gate electrode layer and in contact with the second semiconductor layer, the second semiconductor layer being between the second electrode layer and the third electrode layer (Zhu, Para [0058], third source/drain defining layer surrounding the gate stack, contacting the second channel region; second channel region between the second and third source/drain regions);
a conductive first charge storage layer between the first gate electrode layer and the first semiconductor layer (Zhu, Para [0052]–[0054]; storage function layer between the gate conductor and the active region, but a charge-trapping or ferroelectric material — see Hopkins for the conductive charge-storage limitation); and
a conductive second charge storage layer between the first gate electrode layer and the second semiconductor layer (Zhu, Para [0058], same storage function layer at the second cell along the common gate pillar — conductive nature supplied by Hopkins).
Zhu does not teach that the first and second charge storage layers are conductive. Zhu instead describes its storage function layer as comprising a charge trapping material or a ferroelectric material (Zhu, Para [0052]–[0054]), i.e., a dielectric charge-trap (SONOS-type) or ferroelectric storage medium rather than a conductive floating gate.
However, Hopkins teaches a three-dimensional vertical memory in which each memory cell includes a conductive charge-storage structure — a floating gate (FG) of conductively-doped polysilicon — disposed between a semiconductor pillar and a control gate, with a first dielectric between the floating gate and the semiconductor and a barrier film/dielectric between the floating gate and the control gate. (Hopkins, FIG. 3; claims 1, 6, 11–12.) Hopkins teaches that a conductive floating gate provides a known nonvolatile charge-storage mechanism enabling charge-based programming and retention, and that a planar, aligned floating-gate configuration improves gate-coupling uniformity and program/erase performance. (Hopkins, FIG. 4 and accompanying description.)
It would have been obvious before the effective filing date to configure Zhu’s storage function layer as a conductive floating gate, as taught by Hopkins, because doing so is a combination of prior-art elements according to known methods, and a simple substitution of one known charge-storage medium for another, to obtain the predictable result of nonvolatile charge storage, with a reasonable expectation of success (Hopkins). See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007); MPEP § 2143 (B).
Regarding claim 2, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 1, further comprising:
an insulating layer surrounding the first semiconductor layer (Zhu, Para [0050], [0067], [0079]; FIG. 5, isolation layer / interlayer dielectric).
Regarding claim 3, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 1, further comprising:
a first insulating film between the first charge storage layer and the first semiconductor layer (Hopkins, claims 1, 5–6; FIG. 3, first dielectric / tunnel oxide 108 between the floating gate and the semiconductor pillar; see also Zhu, Para [0054], tunneling layer); and
a second insulating film between the first charge storage layer and the first gate electrode layer (Hopkins, claims 1, 5–6; FIG. 3, second dielectric / barrier film between the floating gate and the control gate; see also Zhu, Para [0054], isolation layer).
Regarding claim 4, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 1, wherein the first electrode layer is metal (Zhu, Para [0071], [0079]–[0080], source/drain and interconnection structures may be metal, e.g., tungsten (W); simple substitution of a metal electrode yielding predictable results, MPEP § 2143 (B)), and the second electrode layer is metal (Zhu, Para [0071], [0079], second electrode layer likewise may be metal, e.g., tungsten (W)).
Regarding claim 5, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 1, further comprising:
a second gate electrode layer extending in the first direction and spaced, in a second direction intersecting the first direction, from the first gate electrode layer (Zhu, Para [0022]–[0023], [0084]; FIG. 2(a); FIG. 34(a), plurality of gate stack pillars spaced in the second direction);
a third semiconductor layer surrounding the second gate electrode layer, the third semiconductor layer being between the first electrode layer and the second electrode layer and in contact with the first electrode layer and the second electrode layer (Zhu, Para [0056]–[0058], [0084], channel region of a neighboring gate pillar between and contacting the first and second source/drain defining layers);
a fourth semiconductor layer in the first direction from the third semiconductor layer, the fourth semiconductor layer surrounding the second gate electrode layer and being between the second electrode layer and the third electrode layer and in contact with the second electrode layer and the third electrode layer (Zhu, Para [0058], [0084], upper channel region of the neighboring gate pillar between and contacting the second and third source/drain defining layers);
a conductive third charge storage layer between the second gate electrode layer and the third semiconductor layer (Zhu, Para [0052]–[0054], [0058], storage function layer of the neighboring pillar — conductive nature supplied by Hopkins); and
a conductive fourth charge storage layer between the second gate electrode layer and the fourth semiconductor layer (Zhu, Para [0058], storage function layer at the upper cell of the neighboring pillar — conductive nature supplied by Hopkins).
Regarding claim 6, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 5, further comprising:
a first wiring in the first direction from the first electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), interconnection/source line above the first source/drain defining layer);
a first conductive layer between the first electrode layer and the first wiring and extending in the first direction, the first conductive layer being electrically connected to the first electrode layer and the first wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), source-line contact / conductive contact electrically connecting the first electrode layer and the first wiring);
a second wiring in the first direction from the second electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), bit-line/interconnection above the second source/drain defining layer);
a second conductive layer between the second electrode layer and the second wiring and extending in the first direction, the second conductive layer being electrically connected to the second electrode layer and the second wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), conductive contact connecting the second electrode layer and the second wiring);
a third wiring in the first direction from the third electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), interconnection above the third source/drain defining layer); and
a third conductive layer between the third electrode layer and the third wiring and extending in the first direction, the third conductive layer being electrically connected to the third electrode layer and the third wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), conductive contact connecting the third electrode layer and the third wiring).
Regarding claim 7, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 6, wherein
a distance between the first conductive layer and the first gate electrode layer is less than a distance between the first conductive layer and the second gate electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), staggered contact layout — first conductive layer nearer the first gate pillar than the second);
a distance between the second conductive layer and the first gate electrode layer is greater than a distance between the second conductive layer and the second gate electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), second conductive layer farther from the first gate pillar than from the second); and
a distance between the third conductive layer and the first gate electrode layer is less than a distance between the third conductive layer and the second gate electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), third conductive layer nearer the first gate pillar than the second).
Regarding claim 8, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 5, further comprising:
a third gate electrode layer extending in the first direction, the third gate electrode layer being spaced, in a third direction intersecting the first direction and the second direction, from the first gate electrode layer (Zhu, Para [0022]–[0023], [0084]; FIG. 2(a), gate stack pillar spaced in the third direction);
a fifth semiconductor layer surrounding the third gate electrode layer, the fifth semiconductor layer being between the first electrode layer and the second electrode layer and in contact with the first electrode layer and the second electrode layer (Zhu, Para [0056]–[0058], [0084], channel region of the third pillar between and contacting the first and second source/drain defining layers);
a sixth semiconductor layer in the first direction from the fifth semiconductor layer and surrounding the third gate electrode layer, the sixth semiconductor layer being between the second electrode layer and the third electrode layer and in contact with the second electrode layer and the third electrode layer (Zhu, Para [0058], [0084], upper channel region surrounding the third gate pillar);
a conductive fifth charge storage layer between the third gate electrode layer and the fifth semiconductor layer (Zhu, Para [0052]–[0054], [0058], [0084], storage function layer of the third-direction pillar — conductive nature supplied by Hopkins); and
a conductive sixth charge storage layer between the third gate electrode layer and the sixth semiconductor layer (Zhu, Para [0058], [0084], storage function layer at the upper cell of the third-direction pillar — conductive nature supplied by Hopkins).
Regarding claim 9, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 8, further comprising:
a first gate electrode wiring extending in the third direction (Zhu, Para [0080]; FIG. 40, word line WL connected to the gate conductor via contact, extending in the third direction);
a second gate electrode wiring extending in the third direction (Zhu, Para [0080]; FIG. 40, further word line extending in the third direction);
a first transistor between the first gate electrode wiring and the first gate electrode layer, the first transistor being electrically connected to the first gate electrode wiring and the first gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the word line and the first gate pillar; providing a discrete select transistor is an art-recognized expedient, MPEP § 2143 (B));
a second transistor between the second gate electrode wiring and the second gate electrode layer, the second transistor being electrically connected to the second gate electrode wiring and the second gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the second word line and the second gate pillar, MPEP § 2143 (B)); and
a third transistor between the first gate electrode wiring and the third gate electrode layer, the third transistor being electrically connected to the first gate electrode wiring and the third gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the first word line and the third gate pillar, MPEP § 2143 (B)).
Regarding claim 10, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 1, further comprising:
a second gate electrode layer extending in the first direction and spaced, in a second direction intersecting the first direction, from the first gate electrode layer (Zhu, Para [0022]–[0023], [0084]; FIG. 2(a); FIG. 34(a), plurality of gate stack pillars spaced in the second direction);
a third semiconductor layer surrounding the second gate electrode layer, the third semiconductor layer being between the first electrode layer and the second electrode layer and in contact with the first electrode layer and the second electrode layer (Zhu, Para [0056]–[0058], [0084], channel region of a neighboring gate pillar between and contacting the first and second source/drain defining layers);
a fourth semiconductor layer in the first direction from the third semiconductor layer and surrounding the second gate electrode layer, the fourth semiconductor layer being between the second electrode layer and the third electrode layer and in contact with the second electrode layer and the third electrode layer (Zhu, Para [0058], [0084], upper channel region of the neighboring pillar between and contacting the second and third source/drain defining layers);
a conductive third charge storage layer between the second gate electrode layer and the third semiconductor layer (Zhu, Para [0052]–[0054], [0058], storage function layer of the neighboring pillar — conductive nature supplied by Hopkins);
a conductive fourth charge storage layer between the second gate electrode layer and the fourth semiconductor layer (Zhu, Para [0058], storage function layer at the upper cell of the neighboring pillar — conductive nature supplied by Hopkins);
a third gate electrode layer extending in the first direction and spaced, in a third direction intersecting the first direction and the second direction, from the first gate electrode layer (Zhu, Para [0022]–[0023], [0084]; FIG. 2(a); FIG. 34(a), gate stack pillar spaced in the third direction);
a fifth semiconductor layer surrounding the third gate electrode layer (Zhu, Para [0056]–[0058], [0084], channel region of the third pillar between and contacting the first and second source/drain defining layers);
a sixth semiconductor layer in the first direction from the fifth semiconductor layer and surrounding the third gate electrode layer (Zhu, Para [0058], [0084], upper channel region surrounding the third gate pillar);
a fourth electrode layer spaced from the first electrode layer in the third direction, the fourth electrode layer surrounding the third gate electrode layer and in contact with the fifth semiconductor layer (Zhu, Para [0058], [0084], source/drain defining layer of the third-direction pillar surrounding the third gate pillar and contacting the fifth channel region);
a fifth electrode layer spaced from the second electrode layer in the third direction, the fifth electrode layer surrounding the third gate electrode layer and in contact with the fifth semiconductor layer and the sixth semiconductor layer, the fifth semiconductor layer being between the fourth electrode layer and the fifth electrode layer (Zhu, Para [0058], [0084], source/drain defining layer surrounding the third gate pillar, contacting the fifth and sixth channel regions; fifth channel region between the fourth and fifth electrode layers);
a sixth electrode layer spaced from the third electrode layer in the third direction, the sixth electrode layer surrounding the third gate electrode layer and in contact with the sixth semiconductor layer, the sixth semiconductor layer being between the fifth electrode layer and the sixth electrode layer (Zhu, Para [0058], [0084], source/drain defining layer surrounding the third gate pillar, contacting the sixth channel region; sixth channel region between the fifth and sixth electrode layers);
a conductive fifth charge storage layer between the third gate electrode layer and the fifth semiconductor layer (Zhu, Para [0052]–[0054], [0058], [0084], storage function layer of the third-direction pillar — conductive nature supplied by Hopkins); and
a conductive sixth charge storage layer between the third gate electrode layer and the sixth semiconductor layer (Zhu, Para [0058], [0084], storage function layer at the upper cell of the third-direction pillar — conductive nature supplied by Hopkins).
Regarding claim 11, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 10, further comprising:
a first wiring in the first direction from the first electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), interconnection/source line above the first source/drain defining layer);
a first conductive layer between the first electrode layer and the first wiring, the first conductive layer extending in the first direction and electrically connected to the first electrode layer and the first wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), conductive contact connecting the first electrode layer and the first wiring);
a second wiring in the first direction from the second electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), bit-line/interconnection above the second source/drain defining layer);
a second conductive layer between the second electrode layer and the second wiring, the second conductive layer extending in the first direction and electrically connected to the second electrode layer and the second wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), conductive contact connecting the second electrode layer and the second wiring);
a third wiring in the first direction from the third electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), interconnection above the third source/drain defining layer);
a third conductive layer between the third electrode layer and the third wiring, the third conductive layer extending in the first direction and electrically connected to the third electrode layer and the third wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), conductive contact connecting the third electrode layer and the third wiring);
a fourth wiring in the first direction from the fourth electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), interconnection above the fourth electrode layer);
a fourth conductive layer between the fourth electrode layer and the fourth wiring, the fourth conductive layer extending in the first direction and electrically connected to the fourth electrode layer and the fourth wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), conductive contact connecting the fourth electrode layer and the fourth wiring);
a fifth wiring in the first direction from the fifth electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), interconnection above the fifth electrode layer);
a fifth conductive layer between the fifth electrode layer and the fifth wiring, the fifth conductive layer extending in the first direction and electrically connected to the fifth electrode layer and the fifth wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), conductive contact connecting the fifth electrode layer and the fifth wiring);
a sixth wiring in the first direction from the sixth electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), interconnection above the sixth electrode layer); and
a sixth conductive layer between the sixth electrode layer and the sixth wiring, the sixth conductive layer extending in the first direction and electrically connected to the sixth electrode layer and the sixth wiring (Zhu, Para [0079]–[0080]; FIG. 14(a), conductive contact connecting the sixth electrode layer and the sixth wiring).
Regarding claim 12, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 11, wherein
a distance between the first conductive layer and the first gate electrode layer is less than a distance between the first conductive layer and the second gate electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), staggered contact layout — first conductive layer nearer the first gate pillar than the second);
a distance between the second conductive layer and the first gate electrode layer is greater than a distance between the second conductive layer and the second gate electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), second conductive layer farther from the first gate pillar than from the second); and
a distance between the third conductive layer and the first gate electrode layer is less than a distance between the third conductive layer and the second gate electrode layer (Zhu, Para [0079]–[0080]; FIG. 14(a), third conductive layer nearer the first gate pillar than the second).
Regarding claim 13, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 11, further comprising:
a first gate electrode wiring extending in the third direction (Zhu, Para [0080]; FIG. 40, word line WL connected to the gate conductor via contact, extending in the third direction);
a second gate electrode wiring extending in the third direction (Zhu, Para [0080]; FIG. 40, further word line extending in the third direction);
a first transistor between the first gate electrode wiring and the first gate electrode layer and electrically connected to the first gate electrode wiring and the first gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the word line and the first gate pillar, MPEP § 2143 (B));
a second transistor between the second gate electrode wiring and the second gate electrode layer and electrically connected to the second gate electrode wiring and the second gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the second word line and the second gate pillar, MPEP § 2143 (B)); and
a third transistor between the first gate electrode wiring and the third gate electrode layer and electrically connected to the first gate electrode wiring and the third gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the first word line and the third gate pillar, MPEP § 2143 (B)).
Regarding claim 14, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 10, further comprising:
a first gate electrode wiring extending in the third direction (Zhu, Para [0080]; FIG. 40, word line WL connected to the gate conductor via contact, extending in the third direction);
a second gate electrode wiring extending in the third direction (Zhu, Para [0080]; FIG. 40, further word line extending in the third direction);
a first transistor between the first gate electrode wiring and the first gate electrode layer and electrically connected to the first gate electrode wiring and the first gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the word line and the first gate pillar, MPEP § 2143 (B));
a second transistor between the second gate electrode wiring and the second gate electrode layer and electrically connected to the second gate electrode wiring and the second gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the second word line and the second gate pillar, MPEP § 2143 (B)); and
a third transistor between the first gate electrode wiring and the third gate electrode layer and electrically connected to the first gate electrode wiring and the third gate electrode layer (Zhu, Para [0080]; FIG. 40, select/switching device connecting the first word line and the third gate pillar, MPEP § 2143 (B)).
Regarding claim 19, Zhu teaches a semiconductor memory device (Zhu, Para [0002], a NOR-type storage device), comprising:
a plurality of gate electrode pillars, each extending in a first direction and spaced from each other in second and third directions perpendicular to the first direction (Zhu, Para [0022]–[0023], [0084]; FIG. 2(a); FIG. 34(a), plurality of gate stack pillars spaced in the second and third directions), wherein
each respective gate electrode pillar has (Zhu, Para [0056]–[0058]; FIG. 6):
a first semiconductor layer surrounding the gate electrode pillar (Zhu, Para [0056], [0101]; FIG. 6, active region / first channel region surrounding the gate pillar);
a second semiconductor layer in the first direction from the first semiconductor layer and surrounding the gate electrode pillar (Zhu, Para [0056], [0058], second channel region surrounding the gate pillar, vertically spaced);
a first electrode layer surrounding the gate electrode pillar and in contact with the first semiconductor layer (Zhu, Para [0056]–[0058]; FIG. 6, first source/drain defining layer surrounding the pillar, contacting the first channel region);
a second electrode layer in the first direction from the first electrode layer, the second electrode layer surrounding the gate electrode pillar and in contact with the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being between the first electrode layer and the second electrode layer (Zhu, Para [0058], [0024], second source/drain defining layer surrounding the gate stack, contacting and shared by both channel regions; first channel region between the first and second source/drain regions);
a third electrode layer in the first direction from the second electrode layer, the third electrode layer surrounding the gate electrode pillar and in contact with the second semiconductor layer, the second semiconductor layer being between the second electrode layer and the third electrode layer (Zhu, Para [0058]; FIG. 6, third source/drain defining layer surrounding the gate pillar, contacting the second channel region; second channel region between the second and third electrode layers);
a conductive first charge storage layer between the gate electrode pillar and the first semiconductor layer (Zhu, Para [0052]–[0054], storage function layer — conductive nature supplied by Hopkins); and
a conductive second charge storage layer between the gate electrode pillar and the second semiconductor layer (Zhu, Para [0058], storage function layer at the second cell — conductive nature supplied by Hopkins).
Zhu does not teach that the first and second charge storage layers are conductive. Zhu instead describes its storage function layer as comprising a charge trapping material or a ferroelectric material (Zhu, Para [0052]–[0054]), i.e., a dielectric charge-trap (SONOS-type) or ferroelectric storage medium rather than a conductive floating gate.
However, Hopkins teaches a three-dimensional vertical memory in which each memory cell includes a conductive charge-storage structure — a conductively-doped polysilicon floating gate — disposed between a semiconductor pillar and a control gate, with a first dielectric between the floating gate and the semiconductor and a barrier film between the floating gate and the control gate. (Hopkins, FIG. 3; claims 1, 6, 11–12.) Hopkins teaches that a conductive floating gate provides a known nonvolatile charge-storage mechanism enabling charge-based programming and retention, and that a planar, aligned floating-gate configuration improves gate-coupling uniformity and program/erase performance. (Hopkins, FIG. 4.)
It would have been obvious before the effective filing date to configure Zhu’s storage function layer as a conductive floating gate, as taught by Hopkins, for the same reasons set forth for claim 1 — a combination of prior-art elements and a simple substitution of known charge-storage media to obtain predictable results (Hopkins). See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007); MPEP § 2143 (B).
Regarding claim 20, Zhu in view of Hopkins teaches the semiconductor memory device according to claim 19, wherein the first electrode layer is metal (Zhu, Para [0071], [0079], first and second electrode layers may be metal, e.g., tungsten (W); see claim-4 rationale, MPEP § 2143 (B)), and the second electrode layer is metal (Zhu, Para [0071], [0079], second electrode layer likewise may be metal, e.g., tungsten (W)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 271-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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