Prosecution Insights
Last updated: April 19, 2026
Application No. 18/459,398

MANAGING CONDUCTIVE CONNECTIONS FOR SEMICONDUCTIVE DEVICES

Non-Final OA §102§103§112
Filed
Aug 31, 2023
Examiner
LUKE, DANIEL M
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co. Ltd.
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
91%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allow Rate
478 granted / 678 resolved
+2.5% vs TC avg
Strong +20% interview lift
Without
With
+20.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
36 currently pending
Career history
714
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.0%
+7.0% vs TC avg
§102
27.3%
-12.7% vs TC avg
§112
22.9%
-17.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 678 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This office action is in response to the election filed 12/19/2025. Currently, claims 1-20 are pending. Of these, claims 1-11 have been withdrawn from consideration. Election/Restrictions Applicant’s election without traverse of claims 12-20 is acknowledged. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “325” in FIG. 3B and “344” in FIG. 3G. Furthermore, the drawings are objected to because the layer above “362” in FIG. 3F is unlabeled and is not described in the specification. Moreover, “362” points to two different layers in FIG. 3F and 3G, respectively. And finally, the drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “wherein conductive material is absent between the conductive connection structure and the array structure” must be shown or the feature(s) canceled from the claim(s). The drawings only show embodiments where a connection structure 340 is present between the conductive connection structure 350 and the array structure 330 (see e.g. FIG. 3G). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 20 recites the limitation “to be in contact”, implying that it is intended to be in contact but is not at present in contact. Deleting “to be” would overcome this rejection. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 12-17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2021/0375912, cited in IDS). Pertaining to claim 12, Zhang shows, with reference to FIG. 4O, a semiconductor device, comprising: an array structure comprising a conductive layer (464 and/or 478) coupled to a plurality of strings of memory cells (in stack 430); a conductive connection structure positioned separately from the array structure, the conductive connection structure comprising a plurality of conductive connections (438, 440); and a conductive pad layer (446) arranged above the array structure and the conductive connection structure (in an orientation that is upside-down relative to the depiction in FIG. 4O), the conductive pad layer comprising a plurality of conductive pads (unlabeled) coupled to a portion of the conductive layer and each of the plurality of conductive connections through corresponding conductive vias (unlabeled, between 438/439/440 and 446), wherein the plurality of conductive connections are separated by an isolating material (unlabeled light gray bulk material) filled in the conductive connection structure. Pertaining to claim 13, Zhang shows the corresponding conductive vias are separated and isolated by the isolating material filled between the conductive pad layer, the array structure, and the conductive connection structure (FIG. 4O). Pertaining to claim 14, Zhang shows conductive material is absent between the conductive connection structure and the array structure (FIG. 4O). Pertaining to claim 15, Zhang shows conductive material is absent between the plurality of conductive connections in the conductive connection structure (FIG. 4O). Pertaining to claim 16, Zhang shows a connection angle between the conductive pad layer and at least one of the respective conductive vias is about 90 degrees (FIG. 4O). Pertaining to claim 17, Zhang shows the array structure and the conductive connection structure are integrated in a first die (see FIG. 4F), and wherein the semiconductor device further comprises a second die (comprising 452) integrated with the first die, and wherein at least one of the plurality of conductive connections is coupled to a control circuit in the second die (para. [0155], [0035]; FIG. 4O). Pertaining to claim 19, Zhang shows a system, comprising: a memory device comprising: an array structure comprising a conductive layer (464 and/or 478) coupled to a plurality of strings of memory cells (in stack 430); a conductive connection structure positioned separately from the array structure, the conductive connection structure comprising a plurality of conductive connections (438, 440), wherein the plurality of conductive connections are separated by an isolating material (unlabeled light gray bulk material) filled in the conductive connection structure; and a conductive pad layer (446) arranged above the array structure and the conductive connection structure (in an orientation that is upside-down relative to the depiction in FIG. 4O), the conductive pad layer comprising a plurality of conductive pads (unlabeled) coupled to a portion of the conductive layer and each of the plurality of conductive connections through corresponding conductive vias (unlabeled, between 438/439/440 and 446); and a controller (comprising 452) coupled to the memory device and configured to control the memory device ([0155], [0035]; FIG. 4O). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Wu et al. (US 11,094,653). Zhang shows the devices of claims 12 and 19, wherein each of the plurality of conductive pads is coupled to at least one of the corresponding conductive vias (FIG. 4O). Zhang fails to show a cover layer on top of the conductive pad layer, wherein the cover layer comprises a plurality of pad openings on top of the plurality of conductive pads in the conductive pad layer (both claims 18 and 20), and a plurality of conductive interconnections through a cover layer on top of the conductive pad layer to be in contact with the plurality of conductive pads in the conductive pad layer, wherein the controller is coupled to the memory device through at least one of the plurality of conductive interconnections (claim 20). However, Wu teaches in FIG. 3 and 7-8 that, for a similar device, a cover layer 990 is formed over the pad layer such that openings 992 in the cover layer are over pads 988, allowing for interconnections 788 from a controller die 700 to contact the pads 988 of the memory die 900. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Zhang to have the cover layer taught by Wu, with the motivation that the quality of metal-to-metal bonding is enhanced (col. 17, lines 11-17). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yada et al. (US 10,957,680) discloses an invention similar to Applicant’s. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL LUKE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Aug 31, 2023
Application Filed
Jan 09, 2026
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604725
INTERLEVEL DIELECTRIC STRUCTURE IN SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12598977
FILL OF VIAS IN SINGLE AND DUAL DAMASCENE STRUCTURES USING SELF-ASSEMBLED MONOLAYER
2y 5m to grant Granted Apr 07, 2026
Patent 12575310
DISPLAY APPARATUS HAVING A REPAIR WIRING
2y 5m to grant Granted Mar 10, 2026
Patent 12568815
WIRINGS FOR SEMICONDUCTOR DEVICE ARRANGED AT DIFFERENT INTERVALS AND HAVING DIFFERENT WIDTHS
2y 5m to grant Granted Mar 03, 2026
Patent 12564025
Interconnect with Redeposited Metal Capping and Method Forming Same
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
91%
With Interview (+20.5%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 678 resolved cases by this examiner. Grant probability derived from career allow rate.

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