DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note: a III-nitride transistor is a type of transistor made from a compound semiconductor containing elements from Group III of the periodic table (like gallium, indium, or aluminum) and nitrogen. These transistors are used in high-frequency and high-power electronic devices due to their excellent properties, such as a wide bandgap, high electron mobility, and high breakdown voltage. They are essential for applications like fast communication systems and efficient power electronics.
Drawings
The drawings are objected to because:
Please, change “first thermal substrate 224” in figure 1 to - - first thermal substrate 244 - - for correct typo error.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-31, 36-43 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Wu (U.S. 2013/0222045), hereafter Wu.
As to claim 21, Wu discloses a power conversion module (para-0039+) comprising:
a first daughterboard (65, para-0040) coupled to first and second pads (not shown, the metal layer 81 included pads, para-0051) on a motherboard (85), the first daughterboard (65) comprising a high side transistor (60, para-0039) for the power conversion module; and
a second daughterboard (75, para-0040) coupled to third and fourth pads (not label, but the metal layer 82 included pads, para-0051) on the mother board (85), the second daughterboard (75) comprising a low side transistor (70, para-0039) for the power conversion module.
As to claim 22, Wu discloses the first daughterboard (65) and the second daughter board (75) are mounted on the mother board (85).
As to claim 23, Wu discloses the first daughterboard (65) is mounted on a first side (top side) of the motherboard (85) and the second daughterboard (75) is mounted on a second side (bottom side) of the mother board.
As to claim 24, Wu discloses the first and second daughterboards (65, 75) have the same footprint.
As to claim 25, Wu discloses a plane perpendicular to the first and second surfaces (top and bottom surfaces) of the motherboard (85) intersects the high side transistor (60) and the low side transistor (70).
As to claim 26, Wu discloses the high side transistor (60) and the low side transistor (70) are gallium nitride (GaN) field effect transistors (FETs), (III-nitride transistor).
As to claim 27, Wu discloses in figure 6 the high side transistor (60) is a component of an integrated circuit (IC) chip mounted on the first daughterboard (65) and the low side transistor (70) is a component of an IC chip mounted on the second daughterboard (75).
As to claim 28, Wu discloses the high side transistor (60) is formed on a first die integrated with the first daughterboard (65) and the low side transistor (70) is formed on a second die integrated with the second daughterboard (75).
As to claim 29, Wu discloses an output node (i.e. element 17) on the motherboard (85) is configured to be coupled to a load (28, para-0009+) and an area circumscribed by a current loop for current flowing through a decoupling capacitor (51).
As to claim 30, Wu discloses the high side transistor (60) and the low side transistor (70) define a loop area of the power conversion module.
As to claim 31, Wu discloses a first leg of the current loop (current path) flows in a first direction through the first daughterboard (65), and a second leg of the current loop (current path) flows in a second direction through the second daughterboard (75), the second direction being opposite of the first direction.
As to claim 36, Wu discloses a power conversion module (para-0039+) comprising:
a high side transistor (60) electrically coupled to first and second pads (not label, but the metal layer 81 included the pads) on a motherboard (85);
a low side transistor (70) electrically coupled to third and second pads (not label, but the metal layer 82 included the pads) on the motherboard;
a first thermal substrate (65) thermally coupled to the high side transistor; and
a second thermal substrate (75) thermally coupled to the low side transistor.
As to claim 37, Wu discloses a plane perpendicular to first and second surfaces (top and bottom surfaces) of the motherboard (85) intersects the high side transistor and the low side transistor.
As to claim 38, Wu discloses the high side transistor (60) and the low side transistor (70) are gallium nitride (GaN) field effect transistors (FETs), III- nitride transistor.
As to claim 39, Wu discloses a method for forming a power conversion module, (para-0039+) the method comprising:
coupling a decoupling capacitor (51, para-0048+) on a motherboard (85) to a high side transistor (60) on a first daughterboard (65) and coupling the high side transistor to an output node (i.e. element 17 or 18) of the power conversion module, the output node being situated on the motherboard; and
coupling a low side transistor (70) on a second daughterboard (75) such that the output node is electrically coupled to a low side transistor (70) of the power conversion module and the low side transistor is electrically coupled to the decoupling capacitor (51).
As to claim 40, Wu further comprising: mounting a first thermal substrate (65) on the power conversion module to contact the first daughterboard; and mounting a second thermal substrate (75) on the power conversion module to contact the second daughterboard.
As to claim 41, Wu discloses the first and second daughterboards (65, 75) have the same footprint, figure 6.
As to claim 42, Wu discloses a plane perpendicular to the first and second surfaces (top and bottom surfaces) of the motherboard (85) intersects the high side transistor and the low side transistor.
As to claim 43, Wu discloses the high side transistor (60) and the low side transistor (70) are gallium nitride (GaN) field effect transistors (FETs), III- nitride transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of luebs et al. (U.S. Patent 6,477,058).
Regarding claim 32, Wu discloses all of the limitations of claimed invention except for a first thermal substrate thermally coupled to the first daughterboard; and
a second thermal substrate thermally coupled to the second daughterboard.
Luebs teaches an IC device package (10) as shown in figures 1-3 comprising a first thermal substrate (64) thermally coupled to the first daughterboard (50); and
a second thermal substrate (70) thermally coupled to the second daughterboard (16).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Luebs employed in the module of Wu in order to provide heat dissipating structure.
Allowable Subject Matter
Claims 33-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
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/TUAN T DINH/Primary Examiner, Art Unit 2848