DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21-43 of the application 18/459,419 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,751,353. Although the claims at issue are not identical, they are not patentably distinct from each other because:
U.S. Patent 11,751,353
1. A power conversion module comprising: a motherboard having a first surface and a second surface that opposes the first surface, the motherboard comprising: a first trace that electrically couples a decoupling capacitor mounted on the motherboard to a first pad on the first surface of the motherboard; an output node of the power conversion module; a via extending through the motherboard that electrically couples a second pad on the first surface of the motherboard and a third pad on the second surface of the motherboard coupled to the output node; a second trace that electrically couples a fourth pad on the second surface of the motherboard and the decoupling capacitor; a first daughterboard mounted on the first surface of the motherboard and coupled to the first pad and the second pad of the motherboard, the first daughterboard comprising a high side transistor for the power conversion module; and a second daughterboard mounted on the second surface of the motherboard and coupled to the third pad and the fourth pad of the motherboard, the second daughterboard comprising a low side transistor for the power conversion module.
2. The power conversion module of claim 1, wherein the first daughterboard and the second daughterboard have the same footprint.
3. The power conversion module of claim 2, wherein a plane perpendicular to the first surface and the second surface of the motherboard intersects the high side transistor and the low side transistor.
4. The power conversion module of claim 1, wherein the high side transistor and the low side transistor are gallium nitride (GaN) field effect transistors (FETs).
5. The power conversion module of claim 4, wherein the high side transistor is a component of an integrated circuit (IC) chip mounted on the first daughterboard and the low side transistor is a component of an IC chip mounted on the second daughterboard.
6. The power conversion module of claim 4, wherein the high side transistor is formed on a first die integrated with the first daughterboard and the low side transistor is formed on a second die integrated with the second daughterboard.
7. The power conversion module of claim 1, wherein the output node is configured to be coupled to a load and an area circumscribed by a current loop for current flowing through the decoupling capacitor, the high side transistor and the low side transistor defines a loop area the power conversion module.
8. The power conversion module of claim 7, wherein a first leg of the current loop flows in a first direction through the first daughterboard, and a second leg of the current loop flows in a second direction through the second daughterboard, the second direction being opposite of the first direction.
9. The power conversion module of claim 1, further comprising: a first thermal substrate thermally coupled to the first daughterboard; and a second thermal substrate thermally coupled to the second daughterboard.
10. The power conversion module of claim 9, wherein the first thermal substrate comprises: a direct bonded copper (DBC) patterned layer overlaying a first surface of a ceramic substrate, the DBC patterned layer being in contact with the first daughterboard; and a DBC plate overlaying a second surface of the ceramic layer, the DBC plate being electrically isolated from the first daughterboard and in thermal communication with the first daughterboard.
11. The power conversion module of claim 10, further comprising a housing circumscribing edges of the first thermal substrate and the second thermal substrate.
12. The power conversion module of claim 10, wherein the power conversion module is a direct current (DC) to alternating current (AC) power conversion module or a DC-to-DC power conversion module.
13. A power conversion module comprising: a motherboard having a first surface and a second surface that opposes the first surface, the motherboard comprising: a first trace that electrically couples a decoupling capacitor mounted on the motherboard to a first pad on the first surface of the motherboard; an output node of the power conversion module; a via extending through the motherboard that electrically couples a second pad on the first surface of the motherboard and a third pad on the second surface of the motherboard to the output node; a second trace that electrically couples a fourth pad on the second surface of the motherboard and the decoupling capacitor; a high side transistor electrically coupled to the first pad and the second pad of the first surface of the motherboard; a low side transistor electrically coupled to the third pad and the fourth pad on the second surface of the motherboard; a first thermal substrate thermally coupled to the high side transistor; and a second thermal substrate thermally coupled to the low side transistor.
14. The power conversion module of claim 13, wherein a plane perpendicular to the first surface and the second surface of the motherboard intersects the high side transistor and the low side transistor.
15. The power conversion module of claim 13, wherein the high side transistor and the low side transistor are gallium nitride (GaN) field effect transistors (FETs).
16. A method for forming a power conversion module, the method comprising: mounting a first daughterboard to a first surface of a motherboard such that a first trace of the motherboard electrically couples a decoupling capacitor mounted on the motherboard to a high side transistor of the power conversion module on the first daughterboard and the high side transistor is coupled to an output node of the power conversion module, the output node being situated on the motherboard; and mounting a second daughterboard to a second surface of the motherboard, such that the output node is electrically coupled to a low side transistor of the power conversion module and the low side transistor is electrically coupled to the decoupling capacitor.
17. The method of claim 16, further comprising: mounting a first thermal substrate on the power conversion module to contact the first daughterboard; and mounting a second thermal substrate on the power conversion module to contact the second daughterboard.
18. The method of claim 17, wherein the first daughterboard and the second daughterboard have the same footprint.
19. The method of claim 18, wherein a plane perpendicular to the first surface and the second surface of the motherboard intersects the high side transistor and the low side transistor.
20. The method of claim 19, wherein the high side transistor and the low side transistor are gallium nitride (GaN) field effect transistors (FETs).
Application No.: 18/459419
21. (Original) A power conversion module comprising:
a first daughterboard coupled to a first pad and a second pad on a motherboard, the first daughterboard comprising a high side transistor for the power conversion module; and
a second daughterboard coupled to a third pad and a fourth pad on the mother
board, the second daughterboard comprising a low side transistor for the power conversion module.
22. (Original) The power conversion module of Claim 21, wherein the first
daughterboard and the second daughter board are mounted on the mother board.
23. (Currently amended) The power conversion module of Claim 22, where the first daughterboard is mounted on a first side of the motherboard and the second daughterboard is mounted on a second side of the motherboard.
24. (Original) The power conversion module of claim 21, wherein the first daughterboard and the second daughterboard have the same footprint.
25. (Original) The power conversion module of claim 24, wherein a plane perpendicular to the first surface and the second surface of the motherboard intersects the high side transistor and the low side transistor.
26. (Original) The power conversion module of claim 21, wherein the high side transistor and the low side transistor are gallium nitride (GaN) field effect transistors (FETs).
27. (Original) The power conversion module of claim 26, wherein the high side transistor is a component of an integrated circuit (IC) chip mounted on the first daughterboard and the low side transistor is a component of an IC chip mounted on the second daughterboard.
28. (Original) The power conversion module of claim 26, wherein the high side transistor is formed on a first die integrated with the first daughterboard and the low side transistor is formed on a second die integrated with the second daughterboard.
29. (Original) The power conversion module of claim 21, wherein an output node on the motherboard is configured to be coupled to a load and an area circumscribed by a current loop for current flowing through a decoupling capacitor.
30. (Original) The power conversion module of claim 29, wherein the high side transistor and the low side transistor define a loop area of the power conversion module.
31. (Original) The power conversion module of claim 29, wherein a first leg of the current loop flows in a first direction through the first daughterboard, and a second leg of the current loop flows in a second direction through the second daughterboard, the second direction being opposite of the first direction.
32. (Original) The power conversion module of claim 21, further comprising:
a first thermal substrate thermally coupled to the first daughterboard; and
a second thermal substrate thermally coupled to the second daughterboard.
33. (Currently amended) A power conversion module comprising:
a first daughterboard coupled to a first pad and a second pad on a motherboard, the first daughterboard comprising a high side transistor for the power conversion module;
a second daughterboard coupled to a third pad and a fourth pad on the mother
board, the second daughterboard comprising a low side transistor for the power conversion module;
a first thermal substrate thermally coupled to the first daughterboard, wherein the first thermal substrate comprises:
a direct bonded copper (DBC) patterned layer overlaying a first surface of a
ceramic substrate, the DBC patterned layer being in contact with the first
daughterboard; and
a DBC plate overlaying a second surface of the ceramic layer, the DBC
plate being electrically isolated from the first daughterboard and in thermal
communication with the first daughterboard; and
a second thermal substrate thermally coupled to the second daughterboard.
34. (Original) The power conversion module of claim 33, further comprising a housing circumscribing edges of the first thermal substrate and the second thermal substrate.
35. (Original) The power conversion module of claim 33, wherein the power conversion module is a direct current (DC) to alternating current (AC) power conversion module or a DC-to-DC power conversion module.
36. (Currently amended) A power conversion module comprising:
a high side transistor electrically coupled to a first pad and a second pad on a
motherboard;
a low side transistor electrically coupled to a third pad and a fourth pad on the
motherboard;
a first thermal substrate thermally coupled to the high side transistor and spaced
from the motherboard; and
a second thermal substrate thermally coupled to the low side transistor.
37. (Original) The power conversion module of claim 36, wherein a plane perpendicular to the first surface and the second surface of the motherboard intersects the high side transistor and the low side transistor.
38. (Original) The power conversion module of claim 36, wherein the high side transistor and the low side transistor are gallium nitride (GaN) field effect transistors (FETs).
39. (Currently amended) A method for forming a power conversion module, the method comprising:
coupling a decoupling capacitor on a motherboard to a high side transistor on a first daughterboard and coupling the high side transistor to an output node of the power conversion module, the output node being situated on the motherboard; and
coupling a low side transistor on a second daughterboard such that the output node
is electrically coupled to a low side transistor of the power conversion module and the low side transistor is electrically coupled to the decoupling capacitor; and
coupling a thermal substrate to one of the high side and low side transistors, the
thermal substrate being spaced from the motherboard.
40. (Currently amended) The method of claim 39, further comprising coupling a
second thermal substrate to the other of the high side and low side transistors, the second thermal substrate being spaced from the motherboard
41. (Original) The method of claim 40, wherein the first daughterboard and the second daughterboard have the same footprint.
42. (Original) The method of claim 41, wherein a plane perpendicular to the first surface and the second surface of the motherboard intersects the high side transistor and the low side transistor.
43. (Original) The method of claim 42, wherein the high side transistor and the low side transistor are gallium nitride (GaN) field effect transistors (FETs).
Regarding claims 21-23 of an instant application 18/459,419, claim 1 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claims 21-23 of the instant application.
Regarding claim 24 of the instant application 18/459,419, claim 2 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claim 24 of the instant application.
Regarding claim 25 of the instant application 18/459,419, claim 3 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claim 25 of the instant application.
Regarding claim 26 of the instant application 18/459,419, claim 4 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claim 26 of the instant application.
Regarding claims 27-28 of the instant application 18/459,419, claims 5-6 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claims 27-28 of the instant application.
Regarding claims 29-30 of the instant application 18/459,419, claim 7 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claims 29-30 of the instant application.
Regarding claims 31-32 of the instant application 18/459,419, claims 8-9 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claims 31-32 of the instant application.
Regarding claim 33 of the instant application 18/459,419, claims 1, and 9-10 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claim 33 of the instant application.
Regarding claims 34-35 of the instant application 18/459,419, claims 11-12 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claims 34-35 of the instant application.
Regarding claims 27-28 of the instant application 18/459,419, claims 5-6 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claims 27-28 of the instant application.
Regarding claim 36 of the instant application 18/459,419, claim 13 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claim 36 of the instant application.
Regarding claims 37-88 of the instant application 18/459,419, claims 14-15 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claims 37-38 of the instant application.
Regarding claims 39-43 of the instant application 18/459,419, claims 16-20 of the U.S. Patent 11,751,353 discloses and encompass all the limitations of claims 39-43 of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-31, 36-38, and 44-46 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (‘045) in view of Smith et al. (U.S. 2020/0129974).
As to claims 21-23, Wu discloses a power conversion module (para-0039+) comprising:
a first daughterboard (65, para-0040) coupled to first and second pads (not
shown, the metal layer 81 included pads, para-0051) on a motherboard (85), the first
daughterboard (65) comprising a high side transistor (60, para-0039) for the power conversion module; and
a second daughterboard (75, para-0040) coupled to third and fourth pads (not label, but the metal layer 82 included pads, para-0051) on the mother board (85), the second daughterboard (75) comprising a low side transistor (70, para-0039) for the power conversion module, and the first daughterboard (65) is mounted on a first
side (top side) of the motherboard (85) and the second daughterboard (75) is mounted on a second side (bottom side) of the mother board.
Wu does not specifically disclose first and second pads mounted on a first side (top side) and third and fourth pads mounted on a second side (bottom side) of the motherboard respectively.
Hovis teaches decoupling capacitance arrangements for integrated circuit devices as shown in figure 2 comprising a carrier circuit board (121) coupled on first and second pads (115) of a system circuit board (111) and a power assembly circuit board (140) coupled to third and fourth pads (116) of the system circuit board (111).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Hovis employed in the module of Wu in order to provide electrical connection structure.
As to claim 24, Wu as modified by Hovis discloses the first and second daughterboards (65, 75) have the same footprint.
As to claim 25, Wu as modified by Hovis discloses a plane perpendicular to the first and second surfaces (top and bottom surfaces) of the motherboard (85) intersects the high side transistor (60) and the low side transistor (70).
As to claim 26, Wu as modified by Hovis discloses the high side transistor (60) and the low side transistor (70) are gallium nitride (GaN) field effect transistors (FETs), (III-nitride transistor).
As to claim 27, Wu as modified by Hovis discloses in figure 6 the high side transistor (60) is a component of an integrated circuit (IC) chip mounted on the first daughterboard (65), and the low side transistor (70) is a component of an IC chip mounted on the second daughterboard (75).
As to claim 28, Wu as modified by Hovis discloses the high side transistor (60) is formed on a first die integrated with the first daughterboard (65) and the low side transistor (70) is formed on a second die integrated with the second daughterboard (75).
As to claim 29, Wu as modified by Hovis discloses an output node (i.e. element 17) on the motherboard (85) is configured to be coupled to a load (28, para-0009+) and an area circumscribed by a current loop for current flowing through a decoupling capacitor (51).
As to claim 30, Wu as modified by Hovis discloses the high side transistor (60) and the low side transistor (70) define a loop area of the power conversion module.
As to claim 31, Wu as modified by Hovis discloses a first leg of the current loop (current path) flows in a first direction through the first daughterboard (65), and a second leg of the current loop (current path) flows in a second direction through the second daughterboard (75), the second direction being opposite of the first direction.
As to claim 36, Wu discloses a power conversion module (para-0039+) comprising:
a high side transistor (60) electrically coupled to first and second pads (not label,
but the metal layer 81 included the pads) on a motherboard (85);
a low side transistor (70) electrically coupled to third and second pads (not label,
but the metal layer 82 included the pads) on the motherboard;
a first thermal substrate (65) thermally coupled to the high side transistor; and
a second thermal substrate (75) thermally coupled to the low side transistor.
Wu does not specifically disclose first and second pads mounted on a first side (top side) and third and fourth pads mounted on a second side (bottom side) of the motherboard respectively, and the first thermal substrate is spaced from the mother board.
Hovis teaches decoupling capacitance arrangements for integrated circuit devices as shown in figure 2 comprising a carrier circuit board (121) coupled on first and second pads (115) of a system circuit board (111) and a power assembly circuit board (140) coupled to third and fourth pads (116) of the system circuit board (111), and the carrier circuit board (121) is spaced from the system circuit board (111).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Hovis employed in the module of Wu in order to provide electrical connection structure.
As to claim 37, Wu as modified by Hovis discloses a plane perpendicular to first and second surfaces (top and bottom surfaces) of the motherboard (85) intersects the high side transistor and the low side transistor.
As to claim 38, Wu as modified by Hovis discloses the high side transistor (60) and the low side transistor (70) are gallium nitride (GaN) field effect transistors (FETs), III- nitride transistor.
As to claims 44-45, Wu as modified by Hovis the low side and high side transistors (60, 70) are mounted on the motherboard directly opposite one another.
As to claim 46, Wu as modified by Hovis the second thermal substrate (75) thermally coupled to the low side transistor (70) is spaced from the motherboard.
Claim(s) 39-43, and 47 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of luebs et al. (‘058).
As to claim 39, Wu discloses a method for forming a power conversion module, (para-0039+) the method comprising:
coupling a decoupling capacitor (51, para-0048+) on a motherboard (85) to a high side transistor (60) on a first daughterboard (65) and coupling the high side transistor to an output node (i.e. element 17 or 18) of the power conversion module, the
output node being situated on the motherboard; and
coupling a low side transistor (70) on a second daughterboard (75) such that the
output node is electrically coupled to a low side transistor (70) of the power conversion
module and the low side transistor is electrically coupled to the decoupling capacitor (51);
Wu does not specifically disclose coupling a thermal substrate to one of the high side and low side transistors, and spaced from the motherboard.
Luebs teaches an IC device package (10) as shown in figures 1-3 comprising a first thermal substrate (68) thermally coupled to an IC device (12) of the first daughterboard (50); and spaced from a motherboard (14).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Luebs employed in the module of Wu in order to provide heat dissipating structure.
As to claim 40, Wu as modified by Luebs further comprising: mounting a second thermal substrate (74) to other of the high side and low side transistors, and spaced from the motherboard.
As to claim 41, Wu as modified by Luebs discloses the first and second daughterboards (65, 75) have the same footprint, figure 6.
As to claim 42, Wu as modified by Luebs discloses a plane perpendicular to the first and second surfaces (top and bottom surfaces) of the motherboard (85) intersects the high side transistor and the low side transistor.
As to claim 43, Wu as modified by Luebs discloses the high side transistor (60) and the low side transistor (70) are gallium nitride (GaN) field effect transistors (FETs), III- nitride transistor.
As to claim 47, Wu as modified by Luebs the low side and high side transistors (60, 70) are mounted on the motherboard directly opposite one another.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Hovis, and further in view of luebs et al. (U.S. Patent 6,477,058).
Regarding claim 32, Wu as modified by Hovis discloses all of the limitations of claimed invention except for a first thermal substrate thermally coupled to the first daughterboard; and a second thermal substrate thermally coupled to the second daughterboard.
Luebs teaches an IC device package (10) as shown in figures 1-3 comprising a first thermal substrate (64) thermally coupled to the first daughterboard (50); and a second thermal substrate (70) thermally coupled to the second daughterboard (16).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Luebs employed in the module of Wu and Hovis in order to provide heat dissipating structure.
Allowable Subject Matter
Claims 33-35 are allowed.
The following is an examiner’s statement of reasons for allowance:
Neither the references cited nor the cited references teach, suggest, or in combination of the power conversion module having the first thermal substrate comprises: a direct bonded copper (DBC) patterned layer overlaying a first surface of a ceramic substrate, the DBC patterned layer being in contact with the first daughterboard; and a DBC plate overlaying a second surface of the ceramic layer, the DBC plate being electrically isolated from the first daughterboard and in thermal communication with the first daughterboard (claim 33).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 33-35 would be allowable if rewritten or amended to overcome the rejection(s) of Double Patenting, set forth in this Office action.
Response to Arguments
Applicant’s arguments with respect to claim(s) 21-47 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F.
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/TUAN T DINH/Primary Examiner, Art Unit 2847
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