DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d)
based on an application filed in Korea (KR 10-0111016) on September 01, 2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/01/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 20180166420 A1).
Regarding Claim 1, Park et al. discloses a semiconductor package comprising:
a base substrate 600 (Fig. 4: 600, paragraph 0051);
an interposer 300 disposed on the base substrate 600, wherein the interposer 300 includes a plurality of recesses in a bottom surface thereof (see annotated Fig. 4: 300, 600, recess, paragraph 0051, 0053);
a semiconductor chip 100 disposed on the interposer 300 (Fig. 1: 100, paragraph 0022, 0023);
a plurality of interposer connection terminals between the interposer 300 and the base substrate 600, wherein the plurality of interposer connection terminals electrically connect the interposer 300 to the base substrate 600 (see annotated Fig. 4: interposer connection terminals, 600, 300);
and a first underfill layer 200 disposed between the interposer 300 and the base substrate 600 (Fig. 4: 200, paragraph 0053),
wherein the first underfill layer 200 at least partially surrounds the plurality of interposer connection terminals (see Fig. 4: 200),
wherein the first underfill layer 200 at least partially surrounds a side surface S1 of each of the plurality of recesses and has a slope declining from the bottom surface Sb of the interposer to a top surface of the base substrate 600 (see annotated Fig. 4: 200, S1, Sb, 600).
Regarding Claim 2, Park et al. discloses the semiconductor package of claim 1, wherein each of the plurality of recesses is formed in a lower corner of the interposer 300 and is defined by a first surface S1 and a second surface S2 of the interposer 300, wherein the first and second surfaces S1, S2 extend in different directions from each other, and wherein the second surface S2 of each of the plurality of recesses has a step difference W1 with respect to the bottom surface Sb of the interposer 300 and faces the base substrate 600 (see annotated Fig. 4: S1, S2, Sb, W1, 300, 600).
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Annotated Fig. 4 of Park et al. (US 20180166420 A1)
Regarding Claim 3, Park et al. discloses the semiconductor package of claim 2, wherein the step difference W1 of the second surface S2 is less than or equal to half of a thickness T of the interposer 300 (see annotated Fig. 4: W1, S2, T, 300).
Regarding Claim 4, Park et al. discloses the semiconductor package of claim 2, wherein the first surface S1 of each of the plurality of recesses is further outward than the plurality of interposer connection terminals in a first direction D1 that is parallel with a top surface St of the interposer 300 (see annotated Fig. 4: S1, St, D1).
Regarding Claim 5, Park et al. discloses the semiconductor package of claim 1, wherein a side wall S3 of the interposer 300 protrudes beyond a side wall Su of the first underfill layer 200 in a lateral direction D1 ( see annotated Fig. 4: S3, Su, 200, D1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), as applied to Claim 1 above, further in view of Kim (US 20200020613 A1).
Regarding Claim 6, Park et al. fails to disclose the semiconductor package of claim 1, further comprising a second underfill layer between the base substrate and the interposer, wherein the second underfill layer at least partially surrounds a side surface of the first underfill layer.
However, Kim teaches a semiconductor package comprising a second underfill layer 400 between the base substrate 100 and the interposer 300, wherein the second underfill layer 400 at least partially surrounds a side surface of the first underfill layer 220 (Fig. 1: 400, 100, 300, 220, paragraph 0053)
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Kim in order to have a second underfill layer between the base substrate and the interposer, wherein the second underfill layer at least partially surrounds a side surface of the first underfill layer. Doing so would provide the semiconductor package with enhanced protection from moisture and contaminants rendered by the second underfill layer.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), as applied to Claim 1 above, further in view of Wang et al. (US 20200350261 A1).
Regarding Claim 7, Park et al. fails to disclose the semiconductor package of claim 1, wherein each of the plurality of recesses is defined by a surface of the interposer, wherein the surface of the interposer has a curved profile from the bottom surface of the interposer to a side wall of the interposer.
However, Wang et al. teaches a semiconductor package, wherein each of the plurality of recesses is defined by a surface of the interposer 21, wherein the surface 210 of the interposer 21 has a curved profile from the bottom surface 21a of the interposer to a side wall of the interposer 21 (Fig. 2: 21, 21a, 210, paragraph 0023, 0024).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Wang et al. in order to have each of the plurality of recesses defined by a surface of the interposer, wherein the surface of the interposer has a curved profile from the bottom surface of the interposer to a side wall of the interposer. Doing so would minimize stress concentration at the corners of the interposer, as recognized by Wang et al. (paragraph 0030).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), as applied to Claim 1 above, further in view of Huang et al. (US 20220293508 A1).
Regarding Claim 8, Park et al. fails to disclose the semiconductor package of claim 1, wherein each of the plurality of recesses is defined by a surface of the interposer, wherein the surface of the interposer extends from the bottom surface of the interposer to a side wall of the interposer and is oblique to the bottom surface of the interposer.
However, Huang et al. teaches a semiconductor package, wherein each of the plurality of recesses is defined by a surface 140s4 of the interposer 140B, wherein the surface 140s4 of the interposer 140B extends from the bottom surface 141b of the interposer 140B to a side wall 140s5 of the interposer 140B and is oblique to the bottom surface 141b of the interposer 140B (Fig. 13: 140B, 141b, 140s4, 140s5, paragraph 0044).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Huang et al. in order to have each of the plurality of recesses defined by a surface of the interposer, wherein the surface of the interposer extends from the bottom surface of the interposer to a side wall of the interposer and is oblique to the bottom surface of the interposer. By doing so, the angled corners of the interposer can be eliminated, thereby reducing stress concentration and cracking.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), as applied to Claim 1 above, further in view of Pagaila et al. (US 20120104623 A1).
Regarding Claim 9, Park et al. fails to disclose the semiconductor package of claim 1, wherein each of the plurality of recesses has a stair shape having a plurality of step differences, with respect to the bottom surface of the interposer, increasing toward a side wall of the interposer.
However, Pagaila et al. discloses a semiconductor package, wherein each of the plurality of recesses 154, 150 has a stair shape having a plurality of step differences, with respect to the bottom surface of the interposer 155, increasing toward a side wall of the interposer 155 (Fig. 4c: 150, 154, 155, paragraph 0051).
Note that while Fig. 4c shows the first surfaces 162, 164 of the plurality of recesses being angled, according to paragraph 0051, these surfaces can also be vertical, yielding a similar structure of the claimed invention as shown in Fig. 4 of the instant application.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Pagaila et al. in order to have each of the plurality of recesses have a stair shape having a plurality of step differences, with respect to the bottom surface of the interposer, increasing toward a side wall of the interposer. Doing so would minimize stress concentration at the stepped corners of the interposer.
Claims 10-13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), in view of Kim (US 20200020613 A1) and Huang et al. (US 20220293508 A1).
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary reference but disclosed in the secondary reference(s).
Regarding Claim 10, Park et al. discloses a semiconductor package comprising:
a base substrate 600 (Fig. 4: 600, paragraph 0051);
an interposer 300 disposed on the base substrate 600, wherein the interposer 300 includes a plurality of recesses in a bottom surface thereof (see annotated Fig. 4: 300, 600, recess, paragraph 0051, 0053);
a core die stack 100 disposed on the interposer 300 (Fig. 1: 100, paragraph 0022, 0023);
a plurality of interposer connection terminals disposed between the interposer 300 and the base substrate 600, wherein the plurality of interposer connection terminals electrically connect the interposer 300 to the base substrate 600 (see annotated Fig. 4: interposer connection terminals, 600, 300);
a first underfill layer 200 disposed between the interposer 300 and the base substrate 600 (Fig. 4: 200, paragraph 0053),
wherein the first underfill layer 200 at least partially surrounds the plurality of interposer connection terminals (see Fig. 4: 200),
a second underfill layer disposed between the base substrate and the interposer, wherein the second underfill layer at least partially surrounds a side surface of the first underfill layer,
wherein each of the plurality of recesses is formed in a lower corner of the interposer 300 and is defined by a first surface S1 and a second surface S2 of the interposer 300 (see annotated Fig. 4: S1, S2, 300),
wherein the first and second surfaces S1, S2 extend in different directions D1, D2 from each other (see annotated Fig. 4: S1, S2, D1, D2),
and the second surface S2 of each of the plurality of recesses has a step difference W1 with respect to the bottom surface Sb of the interposer 300 and faces the base substrate 300 (see annotated Fig. 4: S2, W2, Sb, 300),
a side wall S3 of the interposer 300 protrudes beyond a side wall Su of the first underfill layer 200 in a lateral direction D1,
and a width of the second surface is about 800 µm to about 1,200 µm.
Kim discloses a semiconductor package comprising:
a second underfill layer 400 disposed between the base substrate 100 and the interposer 300, wherein the second underfill layer 400 at least partially surrounds a side surface of the first underfill layer 220 (Fig. 1: 400, 100, 300, 220, paragraph 0053)
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Kim in order to have a second underfill layer disposed between the base substrate and the interposer, wherein the second underfill layer at least partially surrounds a side surface of the first underfill layer. Doing so would provide the semiconductor package with enhanced protection from moisture and contaminants rendered by the second underfill layer.
Further, Huang et al. discloses a semiconductor package comprising an interposer 140’, and a width Wm of the second surface S2 is greater than 50 µm (see annotated Fig. 22: Wm, S2, 140’, paragraph 0053).
While Huang et al. fails to explicitly teach a width of about 800 µm to about 1,200 µm, the disclosed range of values overlap with the claimed range. According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Huang et al. in order to have a width of the second surface to be about 800 µm to about 1,200 µm. Doing so would improve the reliability of semiconductor package by relieving corner stress and preventing delamination and cracking at the corners of the interposer, as recognized by Huang et al. (paragraph 0053).
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Annotated Fig. 22 of Huang et al. (US 20220293508 A1)
Regarding Claim 11, Park et al. discloses the semiconductor package of claim 10, wherein a width of a bottom surface of the first underfill layer 200 is less than a width of a top surface of the first underfill layer 200 (see Fig. 4: 200).
Regarding Claim 12, Park et al. discloses the semiconductor package of claim 10, wherein the first underfill layer 200 includes a first underfill layer contact surface S4 contacting the second surface S2 of each of the plurality of recesses (Annotated Fig. 4: 200, S4, S2), but fails to explicitly teach the width W2 of the second surface S2 is at least about 20 µm greater than a width W3 of the first underfill layer contact surface S4.
However, Park et al. teaches the width W2 is greater than the width W3 (see annotated Fig. 4: W2, W3). The difference in width is a result-effective variable that affects the function of the device, such as the underfill flow and coverage or stress distribution and thus can be optimized through routine experimentation. Furthermore, according to MPEP § 2144.05 (II-A), differences in dimensions will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not provided any experimental evidence to demonstrate that the difference in widths renders unexpected results, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have optimized the difference in widths between the second surface and the underfill layer contact surface through routine optimization such that the width of the second surface is at least about 20 µm greater than a width of the first underfill layer contact surface.
Regarding Claim 13, Park et al. discloses the semiconductor package of claim 10, further comprising a plurality of first connection terminals 24 electrically connecting the core die stack 100 to the interposer 300, and wherein the width W2 of the second surface S2 of each of the plurality of recesses is less than a distance W4 in a first direction D1 from the side wall S3 of the interposer 300 to an outermost one of the plurality of first connection terminals 24, wherein the first direction D1 is parallel with a top surface St of the interposer 300 (Fig. 1: 24, 100, annotated Fig. 4: S3, S2, W2, W4, St, 300, paragraph 0023).
Regarding Claim 15, Park et al. discloses the semiconductor package of claim 10, wherein the first underfill layer 200 includes a non-conductive film (NCF) (paragraph 0041).
Regarding Claim 16, the combination of Park et al. and Kim discloses the semiconductor package of claim 15, wherein the second underfill layer (400, as taught by Kim in Fig. 1) covers a portion of the second surface S2 of each of the plurality of recesses (as taught by Park et al., see annotated Fig. 4).
Note that the a portion of the second surface S2 of each of the plurality of recesses is exposed by the underfill 200 (see annotated Fig. 4: 200, S2) and thus, when the second underfill layer 400 of Kim (see Fig. 1: 400) is disposed in the semiconductor package of Park et al., the second underfill layer will cover the exposed portion of the second surface S2 of each of the plurality of recesses.
Regarding Claim 17, Kim discloses the semiconductor package of claim 10, wherein the second underfill layer 400 includes a material different from a material of the first underfill layer 220 (Fig. 1: 220, 400, paragraph 0043, 0054).
Note that according to an embodiment, the first underfill layer 220 may include epoxy resin (paragraph 0043), which is a thermosetting material, and the second underfill layer 400 may include a thermoplastic material (paragraph 0054), which is a different class of material than thermosetting materials.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), in view of Kim (US 20200020613 A1) and Huang et al. (US 20220293508 A1), as applied to Claim 10 above, further in view of second reference Wang et al. (US 20210296261 A1), herein referred to as Wang II.
Regarding Claim 14, the combination of Park et al., Kim and Huang et al. fails to discloses the semiconductor package of claim 10, wherein the step difference of the second surface with respect to the bottom surface of the interposer is about 45 µm to about 65 µm.
However, Wang II discloses a semiconductor package comprising a plurality of recesses A, wherein the step difference H of the second surface 211 with respect to the bottom surface 21a of the interposer 21 is about 61.6 µm (Fig. 2A: A, 211, H, 21, 21a, paragraph 0033, 0036).
Note that while Fig. 2A shows the recess A is obtuse shaped, paragraph 0035 states that the surface 211 can be made horizontal and surface 210 can be made vertical to form a stepped recess similar to Fig. 2 of the instant application. A person of ordinary skill in the art would have recognized that the modified recess A of Fig. 2A with then have a step difference H = 61.6 µm of the second surface 211 with respect to the bottom surface 21a of the interposer 21 (see Fig. 2: H, paragraph 0036).
While Wang II fails to explicitly disclose a range of about 45 µm to about 65 µm, the disclosed value lies overlap the claimed range. According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Wang II in order to have the step difference of the second surface with respect to the bottom surface of the interposer be about 45 µm to about 65 µm. Doing so would ensure sufficient step height is achieved to minimize stress concentration at corners of the interposer.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), in view of Kim (US 20200020613 A1).
Regarding Claim 18, Park et al. discloses a semiconductor package comprising:
a base substrate 600 (Fig. 4: 600, paragraph 0051);
a silicon interposer 300 attached to the base substrate 600, and including a plurality of recesses, (see annotated Fig. 4: 300, 600, recess, paragraph 0051, 0053);
wherein each of the plurality of recesses includes a first surface S1 and a second surface S2, wherein the first surface S1 is substantially perpendicular to a first direction D1, and wherein the second surface S2 has a step difference W1 from a bottom surface Sb of the silicon interposer 300 and faces the base substrate 600 (annotated Fig. 4: S1, S2, W1, D1, 300, 600, Sb);
at least one stack structure 1 attached to the silicon interposer 300 and including a first semiconductor chip 10 and a plurality of second semiconductor chips 100 stacked on the first semiconductor chip 10 in a vertical direction D2 (Fig. 1: 1, 10, 100, annotated Fig. 4: 1, 300, D2, paragraph 0022, 0023)
wherein the first semiconductor chip 10 includes a first semiconductor substrate 21 and a plurality of first through electrodes 25 passing through the first semiconductor substrate 21 (Fig. 1: 10, 21, 25, paragraph 0023),
and wherein each of the plurality of second semiconductor chips 100 includes a second semiconductor substrate 110, 120, 130 and a plurality of second through electrodes 25 electrically connected to the plurality of first through electrodes 25 (Fig. 1: 100, 110, 120, 130, 25);
a plurality of third semiconductor chips 400, 500 attached to the silicon interposer 300 and separated from the at least one stack structure 1 in a horizontal direction D1 (Fig. 4: 1, 400, 500, paragraph 0050);
a first underfill layer 200 disposed between the silicon interposer 300 and the base substrate 600, wherein the first underfill layer 200 bonds the silicon interposer 300 to the base substrate 600 and includes a first underfill layer contact surface S4 contacting the second surface S2 of each of the plurality of recesses (annotated Fig. 4: 200, 300, 600, S4, S2, paragraph 0053);
and a second underfill layer at least partially surrounding a side surface of the first underfill layer,
wherein the step difference W1 of the second surface S2 is less than or equal to half of a thickness T of the silicon interposer 300 (see annotated Fig. 4: W1, S2, T, 300).
Kim discloses a semiconductor package comprising:
a second underfill layer 400 at least partially surrounding a side surface of the first underfill layer 220 (Fig. 1: 400, 100, 300, 220, paragraph 0053)
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Kim in order to have a second underfill layer at least partially surrounding a side surface of the first underfill layer. Doing so would provide the semiconductor package with enhanced protection from moisture and contaminants rendered by the second underfill layer.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), in view of Kim (US 20200020613 A1), as applied to Claim 18 above, further in view of Woo et al. (US 20220238146 A1) and Lee et al. (US 20140048947 A1).
Regarding Claim 19, the combination of Park et al. and Kim et al. teaches the semiconductor package of claim 18, wherein each of the plurality of second semiconductor chips 100 includes a dynamic random access memory (DRAM) die (paragraph 0036), but fails to teach wherein the first semiconductor chip 10 includes a high bandwidth memory (HBM) control die, and wherein at least one of the plurality of third semiconductor chips 400, 500 includes a plurality of functional blocks, and at least another one of the plurality of third semiconductor chips 400, 500 includes one functional block.
However, Woo et al. discloses a semiconductor package PA1 comprising a first semiconductor chip 112, wherein the first semiconductor chip 112 includes a high bandwidth memory (HBM) control die (Fig. 1: 112, PA1, paragraph 0029, 0030).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al., Kim and Woo et al. in order to have the first semiconductor chip include a high bandwidth memory (HBM) control die. By doing so, the semiconductor package can be optimized for high memory bandwidth.
However, Lee et al. discloses a semiconductor package 1000C comprising a plurality of third semiconductor chips 400A, 400C, and wherein at least one of the plurality of third semiconductor chips 400A, 400C includes a plurality of functional blocks 411A, 411C, and at least another one of the plurality of third semiconductor chips 400A, 400C includes one functional block 411A, 411C (Fig. 5: 1000C, 400A, 400C, paragraph 0043-0046).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al., Kim and Lee et al. in order to have at least one of the plurality of third semiconductor chips includes a plurality of functional blocks, and at least another one of the plurality of third semiconductor chips includes one functional block. Doing so would allow a plurality of semiconductor chips having different functions to be included in a single package, thereby implementing a system, as recognized by Lee et al. (paragraph 0006).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20180166420 A1), in view of Kim (US 20200020613 A1), as applied to Claim 18 above, further in view of second reference Wang et al. (US 20210296261 A1), herein referred to as Wang II.
Regarding Claim 20, the combination of Park et al. and Kim et al. fails to explicitly teach the semiconductor package of claim 18, wherein a width of the first surface of each of the plurality of recesses is about 45 µm to about 65 µm, and a width of the second surface of each of the plurality of recesses is at least about 20 µm greater than a width of the first underfill layer contact surface.
However, Wang II discloses a semiconductor package comprising an interposer 21 with a plurality of recesses A, wherein a width H of the first surface 210 of each of the plurality of recesses A is
about 61.6 µm (Fig. 2A: A, 211, H, 21, 21a, paragraph 0033, 0036).
Note that while Fig. 2A shows the recess A is obtuse shaped, paragraph 0035 states that the surface 211 can be made horizontal and surface 210 can be made vertical to form a stepped recess similar to Fig. 2 of the instant application. A person of ordinary skill in the art would have recognized that the modified recess A of Fig. 2A will have a first surface 210 with width H = 61.6 µm with respect to the bottom surface 21a of the interposer 21 (see Fig. 2: H, paragraph 0036).
While Wang II fails to explicitly disclose a range of about 45 µm to about 65 µm, the disclosed value lies overlap the claimed range. According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Park et al. with Wang II in order to have a width of the first surface of each of the plurality of recesses to be about 45 µm to about 65 µm. Doing so would ensure sufficient step height is achieved to minimize stress concentration at corners of the interposer.
Furthermore, Park et al. teaches the width W2 of the second surface S2 of each of the plurality of recesses is greater than the width W3 of the first underfill layer contact surface S4 (see annotated Fig. 4: W2, W3, S2, S4). The difference in width is a result-effective variable that affects the function of the device, such as the underfill flow and coverage or stress distribution and thus can be optimized through routine experimentation. Furthermore, according to MPEP § 2144.05 (II-A), differences in dimensions will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not provided any experimental evidence to demonstrate that the difference in widths renders unexpected results, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have optimized the difference in widths between the second surface and the underfill layer contact surface through routine optimization such that the width of the second surface is at least about 20 µm greater than a width of the first underfill layer contact surface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817
04/30/2026 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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