DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-10 in the “Response To The Restriction Requirement Dated November 13, 2025” filed on January 13, 2026 (hereinafter the “Response”) is acknowledged. Page eight (8) of the Response states:
Please note that claims 1 and 11 have been amended so claim 11 could be rewritten as a dependent claim of claim 1. Further, claim 22 has been drafted so it could be rewritten as a dependent claim from claim 1. Hence, claims 11 and 22 and their corresponding dependent claims fall within the scope of Invention I.
The Examiner respectfully disagrees . The inventions of Group I (original claims 1-10), Group II (which includes original claims 11-13, 16 and new claim 21), and new Group IV (which includes new claims 22-26) are directed to related processes. The related inventions are distinct if: (i) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (ii) the inventions do not overlap in scope, i.e., are mutually exclusive; and (iii) the inventions as claimed are not obvious variants. See, MPEP 806.05(j) and MPEP 802.01.
In the instant case, the inventions as claimed in in Groups I, II and IV are distinct from each other for at least the following reasons. For example, the claimed invention of Group II requires “reducing a thickness of the substrate after forming the first dielectric layer” which neither the claimed invention of Group I nor the claimed invention of new Group IV require. As another example, the claimed invention of new Group IV requires “removing the first dielectric layer and the plurality of conductive structures to expose the plurality of electrodes after the circuit probe test” which neither the claimed invention of Group I nor the claimed invention of Group II require. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to shown them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for at least the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classification;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries); and/or
(d) the prior art applicable to one invention would not likely be applicable to another invention.
Because Applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, non-elected claims 11-13, 16 and 21 of Group II and new claims 22-26 of new Group IV are hereby withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, Applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should Applicant traverse on the ground that the inventions are not patentably distinct, Applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the Examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 8, 2024 was filed before the mailing date of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the IDS is being considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0206893 A1 (Liaw).
Regarding claim 1, Liaw discloses, A method, comprising:
providing an integrated circuit structure (integrated circuit structure (160); FIG. 10; [0042]) comprising:
PNG
media_image1.png
542
732
media_image1.png
Greyscale
a substrate (substrate (102); FIG. 10; [0022]);
a dielectric structure (annotated FIG. 10, above; [0035]) disposed over the substrate (102), the dielectric structure (annotated FIG. 10, above) comprising an upper surface (annotated FIG. 10, above) and including a conductive interconnection structure (conductive interconnection structure (116, 132, and 142); FIG. 10; [0029] and [0034]); and
a plurality of electrodes (plurality of electrodes (134 and 144) FIG. 10; [0034]) disposed over the upper surface of the dielectric structure (annotated FIG. 10, above), wherein at least one of the substrate (102) and the dielectric structure (annotated FIG. 10, above) include at least one electronic circuit (electronic circuit (108); FIG. 1; [0026] and [0042]) coupled to the plurality of electrodes (134 and 144) by way of the conductive interconnection structure (116, 132, and 142 ([0034]));
PNG
media_image2.png
737
1008
media_image2.png
Greyscale
forming a first dielectric layer (annotated FIG. 10, above; [0035]) over the dielectric structure (annotated FIG. 10, above; [0035]) and the plurality of electrodes (134 and 144);
etching ([0002]) the first dielectric layer (annotated FIG. 10, above; [0035]) over each of the plurality of electrodes (134 and 144);
forming a conductive layer (conductive layer (166); FIG. 10; [0046]) over the first dielectric layer (annotated FIG. 10, above) and the plurality of electrodes (134 and 144);
removing at least a portion (annotated FIG. 10, above) of the conductive layer (166) to form a plurality of conductive structures (conductive structures (M6); FIG. 10) over the plurality of electrodes (134 and 144), each of the plurality of conductive structures (M6) contacting (FIG. 10; [0046] and [0053]) a corresponding subset of the plurality of electrodes (134 and 144); and
performing a circuit probe test ([0038] and [0042]) for the integrated circuit structure (160) via the plurality of conductive structures (M6).
Regarding claim 2, Liaw discloses, The method of claim 1, wherein each of the plurality of conductive structures (M6) comprises:
a landing portion (annotated FIG. 10, above) disposed over the first dielectric layer (annotated FIG. 10, above); and
a plurality of conductive columns (conductive columns (136, 146, 162, 164, 172, 174, and 176); FIG. 10; [0034] and [0046]) extending downward from the landing portion (annotated FIG. 10, above) through the first dielectric layer (annotated FIG. 10, above), each of the plurality of conductive columns (136, 146, 162, 164, 172, 174, and 176) contacting (FIG. 10) an associated one of the corresponding subset of the plurality of electrodes (134 and 144).
Regarding claim 5, Liaw discloses, The method of claim 1, wherein:
the integrated circuit structure (160) further comprises at least one electronic circuit (108); FIG. 1; ; [0026] and [0042]) residing in at least one of the substrate (102) and the dielectric structure (annotated FIG. 10, above), the at least one electronic circuit (108) coupled to the plurality of electrodes (134 and 144) ([0034]); and
performing the circuit probe test comprises testing the at least one electronic circuit (108) ([0038] and [0042]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims, the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw.
Regarding claim 3, Liaw does not appear to explicitly disclose, The method of claim 2, wherein a width of each of the plurality of conductive columns is less than or equal to a width of the associated one of the corresponding subset of the plurality of electrodes.
However, there are a finite number of predicable solutions regarding a width of each of the plurality of conductive columns of Liaw relative to a width of the associated one of the corresponding subset of plurality of electrodes—i.e., (i) a width of each of the plurality of conductive columns can be greater than or equal to a width of the associated one of the corresponding subset of plurality of electrodes or (ii) a width of each of the plurality of conductive columns can be less than or equal to a width of the associated one of the corresponding subset of plurality of electrodes—and, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teaching of Liaw before him/her to try each of these predicable solutions with a reasonable expectation of success one of which is wherein a width of each of the plurality of conductive columns (136, 146, 162, 164, 172, 174, and 176) is less than or equal to a width of the associated one of the corresponding subset of the plurality of electrodes (134 and 144), as recited in claim 3. Please see, MPEP 2143(E)—“Obvious To Try” – Choosing From a Finite Number of Identified, Predicable Solutions, With a Reasonable Expectation of Success.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of US 2018/0057356 A1 (Tedeschi).
Regarding claim 4, Liaw does not appear to disclose, The method of claim 1, wherein the corresponding subset of the plurality of electrodes is arranged in a plan view as a two-dimensional electrode array comprising nine electrodes and having a minimum of three rows of electrodes and three columns of electrodes.
However, in analogous art, Tedeschi discloses, that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a plurality of electrodes (plurality of electrodes (210, 212 and 214); FIG. 2; [0043]) can be predicably fabricated as a two-dimensional electrode array comprising nine electrodes (annotated FIG. 2, below) and having a minimum of three rows of electrodes ((210, 212 and 214); annotated FIG. 2, below) and three columns of electrodes ((210, 212 and 214); annotated FIG. 2, below).
PNG
media_image3.png
723
692
media_image3.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Liaw and Tedeschi before him/her that the corresponding subset of the plurality of electrodes (134 and 144) of Liaw could be predicably fabricated as a two-dimensional electrode array arranged in a plan view, as taught by Tedeschi, that comprises nine electrodes and having a minimum of three rows of electrodes and three columns of electrodes, as also taught by Tedeschi, because the subset of the plurality of electrodes (134 and 144) of Liaw would continue to operate in the same manner as electrical conductors. Please see, MPEP 2143(A)—Combining Prior Art Elements According To Known Methods To Yield Predicable Results.
Claim 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of US 2019/0164867 A1 (Hu).
Regarding claim 6, Liaw does not appear to explicitly disclose, The method of claim 1, further comprising:
forming a second dielectric layer over the plurality of conductive structures and the first dielectric layer; and
etching the second dielectric layer over at least a portion of each of the plurality of conductive structures.
However, in analogous art, Hu discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a method may include forming a dielectric layer to electrically isolate a first conductive feature from a second conductive feature ([claim 6]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Liaw and Hu before him/her to form a second dielectric layer over the plurality of conductive structures (M6) and the first dielectric layer (annotated FIG. 10, above) of Liaw, as taught by Hu, to electrically isolate conductive structures (M6) of Liaw from each other, as also taught by Hu and to etch the second dielectric layer over at least a portion of each of the plurality of conductive structures (M6) so that the conductive structures (M6) may be accessed to perform the circuit probe test ([0038] and [0042]) for the integrated circuit structure (160) of Liaw, as recited in claim 1 from which claim 6 depends. See, MPEP 2144(I)—Rational May Be In A Reference, Or Reasoned From Common Knowledge In The Art, Scientific Principles, Art-Recognized Equivalents, Or Legal Precedent—“The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law.”
Regarding claim 7, Liaw in view of Hu discloses, The method of claim 6, wherein an upper surface of the second dielectric layer is higher than an upper surface of each of the plurality of conductive structures (M6) because the etching step of claim 6 removes the second dielectric layer covering at least a portion of each of the plurality of conductive structures (M6), thereby exposing upper surfaces thereof for circuit probe testing causing an upper surface of the second dielectric layer adjacent the plurality of conductive structures (M6) to be higher than the exposed upper surfaces of the plurality of conductive structures (M6) from which the second dielectric layer has been removed by etching.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of US 2018/0122718 A1 (Hisaka).
Regarding claim 8, Liaw does not appear to explicitly disclose, The method of claim 1, further comprising:
forming a first protective film over the dielectric structure and the plurality of electrodes before forming the first dielectric layer, wherein etching the first dielectric layer further comprises etching at least a portion of the first protective film over the plurality of electrodes.
But, in analogous art, Hisaka discloses, that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a protective film may be predicably formed on a semiconductor device to resist moisture ([0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teaching of Liaw and Hisaka before him/her to form a first protective film over the dielectric structure (annotated FIG. 10, above) and the plurality of electrodes (134 and 144) of Liaw before forming the first dielectric layer (annotated FIG. 10, above) thereof to resist moisture, as taught by Hisaka, prior to forming the first dielectric layer of Liaw. See, MPEP 2144(IV)—Rational Different From Applicant’s Is Permissible—"The reason or motivation to modify the reference may often suggest what the inventor has done, but for a different purpose or to solve a different problem. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teaching of Liaw and Hisaka before him/her to etch at least a portion of the first protective film over the plurality of electrodes (134 and 144) of Liaw as part of etching the first dielectric layer of Liaw, to expose at least a portion of the plurality of electrode (134 and 144) for electrical connection thereto. See, MPEP 2144(I), above.
Allowable Subject Matter
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
US 2023/0097793 A1 (Lajoie)—Discloses a method ([0017]), comprising: providing an integrated circuit structure (1600) (FIG. 10) comprising: a substrate (1602); a dielectric structure (1619) disposed over the substrate (1602), the dielectric structure (1619) comprising an upper surface and including a conductive interconnection structure (1624 and 1628);and a plurality of electrodes (1636) disposed over the upper surface of the dielectric structure (1619), wherein at least one of the substrate (1602) and the dielectric structure (1619) include at least one electronic circuit (1622 and 1640) coupled to the plurality of electrodes (1636) by way of the conductive interconnection structure (1624 and 1628). Also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize et ching as a process of the method detailed therein (e.g., [0047] and [0058]).
US 2024/0387328 A1 (Fornara)—Discloses a method ([0004] for forming an integrated circuit structure (100) (FIG. 7) that includes a substrate (102), a dielectric structure (116), a conductive interconnection structure (120), and electronic circuits (105). Also discloses forming a first dielectric layer (152) over the dielectric structure (116) and the conductive interconnection structure (120). Additionally discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize etching as process of the method detailed therein (e.g., [0005).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812