DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 10/12/2023.
Claims 1-20 are pending in this application.
Specification
2. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112:
(a) IN GENERAL.— The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
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(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
4. Claims 8-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
In claim 8: line 6, the phrases “an individual first bit line” and “an individual second bit line” are not clearly defined, and the claim does not particularly point out and distinctly claim the subject matter which the inventor(s) regards as the Applicant’s invention.
It is unclear whether the claimed “an individual first bit line” and “an individual second bit line” are of the “plurality of first bit lines” and the “plurality of second bit lines”, respectively, or they are different and are not among the “plurality of first bit lines” and the “plurality of second bit lines”.
The claim is therefore indefinite.
Claims 9, 11, 15, 18, and 20 are indefinite for similar reasons:
Claim 9: the phrase “an individual word line”,
Claim 11: “an individual switch” and “the first bit line”,
Claim 15: “an individual conductive structure”,
Claim 18: “an individual via”,
Claim 20: “an individual additional conductive structure”.
Claims 9-14, and 16-20 are also indefinite for depending upon claims 8, and 15, respectively.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1, 3, 5-7, 15-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akkaya et al. (US 2023/0274769)
Regarding claim 1, Akkaya discloses an integrated circuit (IC) device, shown in Fig. 5, comprising:
a transistor 502 comprising a source region 506, a drain region 506, a channel region 504, a first electrode 508 over the channel region 504, and a second electrode 510 over the source region 506 or the drain region 506;
a first conductive structure 546 at a first side (lower side) of the channel region 504, the first conductive structure 546 electrically coupled to the second electrode 510 (via the source/drain region 506 and structure 542);
a second conductive structure 518 at a second side (upper side) of the channel region 504, the second side opposing the first side, the second conductive structure 518 electrically coupled to the first electrode 508; and
a third conductive structure 516 or 524 at the second side (upper side) of the channel region 504.
Regarding claim 3, Akkaya discloses the IC device according to claim 1, further comprising:
a via 514 comprising a first end and a second end, the first end of the via connected to the second conductive structure 518, the second end of the via connected to the first electrode 508. See Fig. 5.
Regarding claim 5, Akkaya discloses the IC device according to claim 1, wherein a longitudinal axis of the first conductive structure 546 is parallel to a longitudinal axis of the third conductive structure 516/524. See Fig. 5.
Regarding claim 6, Akkaya discloses the IC device according to claim 1, wherein a longitudinal axis of the first electrode 508 is parallel to a longitudinal axis of the second conductive structure 518. See Fig. 5.
Regarding claim 7, Akkaya discloses the IC device according to claim 1, wherein a longitudinal axis of the second conductive structure is perpendicular to a longitudinal axis of the third conductive structure. See Fig. 5.
Regarding claim 15, Akkaya discloses an integrated circuit (IC) device, comprising:
a semiconductor structure 502 (Fig. 5) having a first longitudinal axis;
a plurality of conductive structures 508, 510 over portions of the semiconductor structure 502, an individual conductive structure 508, 510 having a second longitudinal axis that is perpendicular to the first longitudinal axis;
a first conductive layer 546; and
a second conductive layer 518 electrically coupled to the individual conductive structure 508,
wherein the semiconductor structure 502 or the individual conductive structure 508, 510 is between the first conductive layer 546 and the second conductive layer 518.
Regarding claim 16, Akkaya discloses the IC device according to claim 15, further comprising: a third conductive layer 526 that is closer to the second conductive layer 518 than to the first conductive layer 546. See Fig. 5.
Regarding claim 18, Akkaya discloses the IC device according to claim 15, further comprising:
a plurality of vias 514, an individual via 514 connected to the individual conductive structure 508 and the second conductive layer 518. See Fig. 5.
Regarding claim 19, Akkaya discloses the IC device according to claim 15, wherein the first conductive layer or the second conductive layer comprises a plurality of conductive elements that are in parallel. See Fig. 5.
Regarding claim 20, Akkaya discloses the IC device according to claim 15, further comprising: a plurality of additional conductive structures 508, 510, 512, 542, 544 over different portions of the semiconductor structure, an individual additional conductive structure electrically coupled to the first conductive layer. See Fig. 5.
Allowable Subject Matter
7. Claims 2, and 4 are allowable.
Claims 2, and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed IC device (in addition to the other limitations in the claim) comprising:
Claim 2:
The IC device according to claim 1, further comprising:
a switch electrically coupled to the first conductive structure and the third conductive structure, wherein the first conductive structure is electrically coupled to the third conductive structure when the switch is closed.
Claim 4:
The IC device according to claim 3, further comprising:
an additional transistor comprising an additional first electrode; and
an additional via comprising a first end and a second end, the first end of the additional via connected to the second conductive structure, the second end of the additional via connected to the additional first electrode.
Conclusion
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 September 18, 2026
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