Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 12/30/25 is acknowledged.
No claims are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/30/25.
Claim Objections
Claim 1 is objected to because of the following informalities: Line 6 of claim one says “insulator layers alternately” but should say “conductor lines alternately”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 18 currently states that the first portion is located above the second portion in line three but located below the second portion in lines 4-5). The claim is being interpreted as the first portion is only located above the second portion
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 7-10, 12, 14 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mitsuno et al. (US PGPub 2021/0028189).
Claim 1: Mitsuno teaches (Fig. 21) a memory device comprising: a plurality of insulator layers (56) spaced apart from one another in a first direction; a plurality of conductor layers (24) spaced apart from one another in the first direction, the plurality of insulator layers and the plurality of conductor layers alternately arranged along the first direction; and a memory pillar (MP) extending in the first direction to intersect the plurality of conductor layers, wherein the plurality of conductor layers include a first conductor layer (24) having a first portion and a second portion in contact with the memory pillar, wherein the first portion is recessed relative to the second portion in a second direction intersecting the first direction, and wherein the plurality of insulator layers include a first insulator layer (53) provided on a first surface of the first conductor layer closer to the first portion than the second portion, and a second insulator layer (56) provided on a second surface of the first conductor layer closer to the second portion than the first portion, the second insulator layer being thinner than the first insulator layer in the first direction.
Claim 5: Mitsuno teaches (Fig. 3,21) first conductor layer (WL8) is a lowermost conductor layer among the plurality of conductor layers (24s), and the first portion is located below the second portion.
Claim 7: Mitsuno teaches (Fig. 21) the first conductor layer (25) is an uppermost conductor layer among the plurality of conductor layers, and the first portion is located above the second portion.
Claim 8: Mitsuno teaches (Fig. 3,21) a portion (ST1) of the memory pillar intersecting the first conductor layer (SGD) functions as a select transistor. The sidewall of (UMP) tapers as it increases in the first direction there for the first portion (top) is recessed relative to the second portion bottom.
Claim 9: Mitsuno teaches (Fig. 21) the memory pillar includes a lower portion (LMP), an upper portion (UMP) located above the lower portion, and a coupling portion (JT) coupling between the lower portion and the upper portion, and side surfaces of the coupling portion are deviated from extensions of respective side surfaces of the lower portion and the upper portion.
Claim 10: Mitsuno teaches (Fig. 21) the first conductor layer (WL8) is a lowermost conductor layer intersecting the upper portion (UMP) of the memory pillar among the plurality of conductor layers, and the first portion is located below the second portion.
Claim 12: Mitsuno teaches (Fig. 21) the first conductor layer (WL7) is an uppermost conductor layer intersecting the lower portion of the memory pillar (LMP) among the plurality of conductor layers, and the first portion is located above the second portion. The sidewall of (UMP) tapers as it increases in the first direction there for the first portion (top) is recessed relative to the second portion bottom.
Claim 14: Mitsuno teaches (Fig. 21) the plurality of conductor layers further include a second conductor layer provided on a surface of the second insulator layer opposite to a surface on which the first conductor layer is provided, wherein the second conductor (24) layer includes a third portion and a fourth portion in contact with the memory pillar, wherein the third portion is recessed relative to the fourth portion in the second direction. The memory pillar widens as it extends in the first direction, therefore the word lines are angled so that the top surface is recessed from the second portion along the memory pillar.
Claim 18: Mitsuno teaches (Fig. 21) the third portion is located above the fourth portion when the first portion is located above the second portion, and is located below the fourth portion when the first portion is located below the second portion.
Claim 19: Mitsuno teaches (Fig. 21) the plurality of insulator layers further include a third insulator layer (56) provided on a surface of the second conductor layer closer to the fourth portion than the second portion, and a film thickness of the third insulator layer (56) is substantially equal to a film thickness of the second insulator layer.
Claim 20: Mitsuno teaches (Fig. 21) a diameter of a portion of the memory pillar intersecting the first portion is larger than a diameter of a portion of the memory pillar intersecting the second portion.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-9, 12-14 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Takeda et al. (US PGPub 2022/0302161).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim 1: Takeda teaches (Fig. 5) a memory device comprising: a plurality of insulator layers (7) spaced apart from one another in a first direction; a plurality of conductor layers (6) spaced apart from one another in the first direction, the plurality of insulator layers and the plurality of conductor layers alternately arranged along the first direction; and a memory pillar (4) extending in the first direction to intersect the plurality of conductor layers, wherein the plurality of conductor layers include a first conductor layer having a first portion and a second portion in contact with the memory pillar, wherein the first portion is recessed relative to the second portion in a second direction intersecting the first direction, and wherein the plurality of insulator layers include a first insulator layer (JL) provided on a first surface of the first conductor layer closer to the first portion than the second portion, and a second insulator layer (7) provided on a second surface of the first conductor layer closer to the second portion than the first portion, the second insulator layer being thinner than the first insulator layer in the first direction.
Claim 7: Takeda teaches (Fig. 5) the first conductor layer (DWL1) is an uppermost conductor layer among the plurality of conductor layers (6s in SST1), and the first portion is located above the second portion.
Claim 8: Takeda teaches (Fig. 5) a portion (SDT) of the memory pillar intersecting the first conductor layer (SGD0) functions as a select transistor. The sidewall of (4C) tapers as it increases in the first direction there for the first portion (top) is recessed relative to the second portion bottom.
Claim 9: Takeda teaches (Fig. 5) the memory pillar includes a lower portion (4a), an upper portion (4c) located above the lower portion, and a coupling portion coupling between the lower portion and the upper portion, and side surfaces of the coupling portion (4b) are deviated from extensions of respective side surfaces of the lower portion and the upper portion.
Claim 12: Takeda teaches (Fig. 5) the first conductor layer (DWL1) is an uppermost conductor layer intersecting the lower portion of the memory pillar (4a) among the plurality of conductor layers, and the first portion is located above the second portion.
Claim 13: Takeda teaches (Fig. 5) a portion of the memory pillar intersecting the first conductor layer functions as a dummy cell (DMT1).
Claim 14: Takeda teaches (Fig. 5) the plurality of conductor layers further include a second conductor layer provided on a surface of the second insulator layer opposite to a surface on which the first conductor layer is provided, wherein the second conductor (WL4) layer includes a third portion and a fourth portion in contact with the memory pillar, wherein the third portion is recessed relative to the fourth portion in the second direction.
Claim 18: Takeda teaches (Fig. 5) the third portion is located above the fourth portion when the first portion is located above the second portion, and is located below the fourth portion when the first portion is located below the second portion.
Claim 19: Takeda teaches (Fig. 5) the plurality of insulator layers further include a third insulator layer (7) provided on a surface of the second conductor layer closer to the fourth portion than the second portion, and a film thickness of the third insulator layer (7) is substantially equal to a film thickness of the second insulator layer.
Claim 20: Takeda teaches (Fig. 5) a diameter of a portion of the memory pillar intersecting the first portion is larger than a diameter of a portion of the memory pillar intersecting the second portion.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuno et al. (US PGPub 2021/0028189) or Takeda et al. (US PGPub 2022/0302161) as applied to claim 1 above and further in view of Ishiduki et al. (US PGPub 2009/0230458)
Regarding claim 2, as described above, Mitsuno or Takeda substantially read on the invention as claimed, except Mitsuno or Takeda do not teach an amount of recession of the first portion relative to the second portion is equal to or greater than about 3 nm. Ishiduki teaches an amount of recession of the first portion relative to the second portion is equal to or greater than about 3 nm [0077] to improve device performance [0007-0013]. Since it has been held when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Applicant can rebut a prima facie case of obviousness based on ranges by showing unexpected results or the criticality of the claimed range. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claim. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F. 2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 716.02-716.02(g) for a discussion of criticality and unexpected results. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have determined the amount of recession through routine experimentation to improve device performance as taught by Ishiduki.
Claim 3: Ishiduki teaches [0077, 0007-0013] a film thickness of the first portion is equal to or greater than about 7 nm and equal to or less than about 13 nm.
Claim 4: Ishiduki teaches [0077, 0007-0013] a ratio of a film thickness of the first portion to a sum of the film thickness of the first portion and a film thickness of the second portion is equal to or greater than 35% and equal to or less than 50%.
Claim 15 : Ishiduki teaches [0077, 0007-0013] an amount of recession of the third portion relative to the fourth portion is equal to or greater than about 3 nm.
Claim 16 : Ishiduki teaches [0077, 0007-0013] a film thickness of the third portion is equal to or greater than about 7 nm and equal to or less than about 13 nm.
Claim 17 : Ishiduki teaches [0077, 0007-0013] a ratio of a film thickness of the third portion to a sum of the film thickness of the third portion and a film thickness of the fourth portion is equal to or greater than about 35% and equal to or less than about 50%.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mitsuno et al. (US PGPub 2021/0028189) as applied to claim 1 above and further in view of Nam (US PGPub 2014/0054676)
Regarding claim 6, as described above, Mitsuno substantially read on the invention as claimed, except Mitsuno do not teach a portion of the memory pillar intersecting the first conductor layer functions as a select transistor. Nam teaches (Fig. 1) a portion of the memory pillar (158, 132) intersecting the first conductor layer (169b) functions as a select transistor with the first portion below the second portion to decrease interference [0077]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have had a portion of the memory pillar intersecting the first conductor layer functions as a select transistor with the first portion below the second portion to decrease interference [0077] as taught by Nam.
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuno et al. (US PGPub 2021/0028189) as applied to claim 1 above and further in view of Takeda et al. (US PGPub 2022/0302161)
Regarding claim 11, as described above, Mitsuno substantially read on the invention as claimed, except Mitsuno do not teach a portion of the memory pillar intersecting the first conductor layer functions as a dummy cell. Takeda teaches a portion of the memory pillar intersecting the first conductor layer functions as a dummy cell to reduce back tunnel phenomenon [0091]. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have had a portion of the memory pillar intersecting the first conductor layer functions as a dummy cell to improve device performance as taught Takeda [0091].
Claim 13: Takeda teaches (Fig. 5) a portion of the memory pillar intersecting the first conductor layer functions as a dummy cell (DMT1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814