Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/459,821 filed on January 05, 2026.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
5. Applicant’s election of claims 1-7, 11-16, 20, Species I (Fig. 3), in the reply filed on 01/05/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
6. Claims 8-10, 17-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected device species claims, there being no allowable generic or linking claim.
Specification
7. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “SEMICONDUCTOR PACKAGE COMPRISING REDISTRIBUTION LAYER ON WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) .
Claim Objections
8. Claims 2-5, 7, 14 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or perform proper alignment along with the prior claim languages/phrases:
2. (Currently Amended) The semiconductor package of claim 1, wherein a conductive bump of the conductive bumps contacts a portion of the first redistribution wiring that is exposed by the UBM pad of the UBM pads.
3. (Currently Amended) The semiconductor package of claim 1, wherein a conductive bump of the conductive bumps covers a portion of the first redistribution wiring that is exposed by the UBM pad of the UBM pads.
4. (Currently Amended) The semiconductor package of claim 1, wherein a lower surface of the UBM pad of the UBM pads is bonded to the at least a portion of the first redistribution wiring that is exposed by the opening.
5. (Currently Amended) The semiconductor package of claim 1, wherein the UBM pad of the UBM pads has a diameter of at least,
7. (Currently Amended) The semiconductor package of claim 1, wherein the UBM pad of the UBM pads and the first redistribution wiring include copper, and the conductive bumps include solder.
14. (Currently Amended) The semiconductor package of claim 11, wherein the bonding pad has a diameter of at least,
Appropriate corrections are needed.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
12. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
13. Claims 1-7, 11-16, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. Tsai et al. (US 2014/0264839 A1) in view of Chen et al. (US 2013/0307119 A1).
Regarding independent claim 1, Tsai et al. teaches a semiconductor package (100, para [0013]), comprising (Figs. 1-2):
a semiconductor chip (102, para [0013]) having chip pads (104, para [0013] called contact pad, multiple pads shown in Fig. 2) disposed on a first surface (upper surface) thereof;
a redistribution wiring layer (120 RDL, para [0013]) formed on the first surface (upper surface) of the semiconductor chip (102), wherein the redistribution wiring layer (120) includes at least one insulating layer (124a, para [0025]), redistribution wirings (122b/122a, para [0024]), a protective layer (124b, para [0026]), and an under bump metallurgy (UBM) pad (122c, para [0026]) of UBM pads (multiple UBM pads, see Fig. 2), wherein the at least one insulating layer (124a) is formed on the first surface (upper surface) of the semiconductor chip (102), wherein the redistribution wirings (122b/122a) are provided on the at least one insulating layer (124a) and are electrically connected to the chip pads (104), wherein the protective layer (124b) is provided on the at least one insulating layer (124a) and has an opening (para [0026] insulating material 124b is patterned to form openings over portions of the second portion 122b of the RDL 120) that exposes at least a portion of a first redistribution wiring (122b) of the redistribution wirings (122b/122a), and wherein the under bump metallurgy (UBM) pad (122c) is provided on the at least a portion of the first redistribution wiring (122b) that is exposed by the opening of the protective layer (124b), and
conductive bumps (126) disposed on the UBM pads (122c) of the redistribution wiring layer (120).
Tsai et al. is explicitly silent of disclosing wherein, the under bump metallurgy (UBM) pad that is exposed by the opening of the protective layer and spaced apart from an inner wall of the opening of the protective layer.
Chen et al. teaches wherein (Fig. 13), the under bump metallurgy (UBM) pad (216: 216b, para [0021]) that is exposed by the opening (220a, para [0026]) of the protective layer (220) and spaced apart from an inner wall of the opening (220a) of the protective layer (220).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Chen et al., and modify the opening in the isolation coating with wider opening of Tsai et al., that exposed the UBM layers, in order to mitigate the heat generation in the redistribution layers and UBM pads, thus more reliable the bonding structure.
Regarding claim 2, Tsai et al. and Chen et al. teach all of the limitations of claim 1 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), a conductive bump (126) of the conductive bumps contacts a portion of the first redistribution wiring (122b) that is exposed by a UBM pad (122c) of the UBM pads (122c/122c per Fig. 2).
Regarding claim 3, Tsai et al. and Chen et al. teach all of the limitations of claim 1 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), a conductive bump (126) of the conductive bumps (126, 126 per Fig. 2) covers a portion of the first redistribution wiring (122b) that is exposed by a UBM pad (122c) of the UBM pads.
Regarding claim 4, Tsai et al. and Chen et al. teach all of the limitations of claim 1 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), a lower surface of a UBM pad (122c) of the UBM pads is bonded to the at least a portion of the first redistribution wiring (122b) that is exposed by the opening (para [0026]). diameter
Regarding claim 5, Tsai et al. and Chen et al. teach all of the limitations of claim 1 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), the UBM pad (122c, para [0028]) of the UBM pads has a certain diameter or width compared to conductive material 126.
Even Tsai et al. is explicitly silent of disclosing wherein the UBM pad of the UBM pads has a diameter of at least, 5 μm. It would have been obvious to select intended ‘diameter of UBM pad’ to be within the quoted range of is at least 5 μm, in order to cover the bottom surface of the solder ball or bump, therefore enhance the conductivity. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed diameter or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen diameter or upon another variable recited in a claim, the Applicant must show that the chosen diameter is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 6, Tsai et al. and Chen et al. teach all of the limitations of claim 1 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), the protective layer (124b) includes a photo imagable dielectric (PID) (polymer-3 level, para [0030] which is a photosensitive material).
Regarding claim 7, Tsai et al. and Chen et al. teach all of the limitations of claim 1 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), the UBM pad (122c) of the UBM pads and the first redistribution wiring (122b) include copper (para [0027]), and the conductive bumps (126) include solder (para [0028]).
Regarding independent claim 11, Tsai et al. teaches a semiconductor package (100, para [0013]), comprising (Figs. 1-2):
A semiconductor chip (102, para [0013]) having chip pads (104, para [0013] contact pads) disposed on a first surface (upper surface) thereof;
a redistribution wiring layer (120, para [0013]) covering the first surface (upper surface) of the semiconductor chip (102) and having redistribution wirings (122b/122a, para [0013]) electrically connected to the chip pads (104); and
conductive bumps (126, para [0013] multiple bumps, see Fig. 2) disposed on an outer surface of the redistribution wiring layer (120) and electrically connected to the redistribution wirings (122b/122a),
wherein the redistribution wiring layer (120) includes:
at least one insulating layer (124a, para [0025]) in which the redistribution wirings (122b/122a) are provided;
a protective layer (124b, para [0026]) provided on the at least one insulating layer (124a) and having an opening (para [0026] Insulating material 124b is patterned to form openings over portions of the second portion 122b of the RDL 120) that exposes at least a portion of a first redistribution wiring (122b) among the redistribution wirings (122b/122a); and
a bonding pad (122c, para [0013] called under-bump metallization structure or UBM) provided on the at least a portion of the first redistribution wiring (122b) that is exposed by the opening of the protective layer (124b), and
wherein a conductive bump (126, para [0013]) of the conductive bumps (126, 126, see Fig. 2) is disposed on the bonding pad (122c).
Tsai et al. is explicitly silent of disclosing wherein, the bonding pad that is exposed by the opening of the protective layer and spaced apart from an inner wall of the opening of the protective layer.
Chen et al. teaches wherein (Fig. 13), the under bump metallurgy (UBM) pad (216: 216b, para [0021]) that is exposed by the opening (220a, para [0026]) of the protective layer (220) and spaced apart from an inner wall of the opening (220a) of the protective layer (220).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Chen et al., and modify the opening in the isolation coating with wider opening of Tsai et al., that exposed the UBM layers, in order to mitigate the heat generation in the redistribution layers and UBM pads, thus more reliable the bonding structure.
Regarding claim 12, Tsai et al. and Chen et al. teach all of the limitations of claim 11 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), the conductive bump (126) completely covers a portion of the first redistribution wiring (122b) that is exposed by the bonding pad (122c).
Regarding claim 13, Tsai et al. and Chen et al. teach all of the limitations of claim 11 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), an entire lower surface of the bonding pad (122c) is bonded to the at least a portion of the first redistribution wiring (122c) that is exposed by the opening of the protective layer (124b).
Regarding claim 14, Tsai et al. and Chen et al. teach all of the limitations of claim 11 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), the bonding pad (122c, para [0028]) has a certain diameter or width compared to conductive material 126.
Even Tsai et al. is explicitly silent of disclosing wherein the bonding pad has a diameter of at least, 5 μm. It would have been obvious to select intended ‘diameter of the bonding pad’ to be within the quoted range of is at least 5 μm, in order to cover the bottom surface of the solder ball or bump, therefore enhance the conductivity. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed diameter or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen diameter or upon another variable recited in a claim, the Applicant must show that the chosen diameter is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 15, Tsai et al. and Chen et al. teach all of the limitations of claim 11 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), the protective layer (124b) includes a photo imagable dielectric (PID) (polymer-3 level, para [0030] which is a photosensitive material).
Regarding claim 16, Tsai et al. and Chen et al. teach all of the limitations of claim 11 from which this claim depends.
Tsai et al. teaches wherein (Fig. 1), the bonding pad (122c) and the first redistribution wiring (122b) include copper (para [0027]), and the conductive bumps (126) include solder (para [0028]).
Regarding independent claim 20, Tsai et al. teaches a semiconductor package (100, para [0013]), comprising (Fig. 1):
a redistribution wiring layer (120, para [0013] RDL) having a first surface (bottom surface) and a second surface (upper surface) that is opposite to the first surface, wherein the redistribution wiring layer (120) includes at least one insulating layer (124a, para [0025]) and redistribution wirings (122b/122a, para [0026]) provided in the at least one insulating layer (124a);
a semiconductor chip (102, para [0013]) arranged on the first surface (bottom surface) of the redistribution wiring layer (120) and having chip pads (104, para [0013] contact pads) that are electrically connected to the redistribution wirings (122b/122a); and
outer connection members (126, para [0013] for multiple connection members, see Fig. 2) disposed on the second surface (upper surface) of the redistribution wiring layer (120) and electrically connected to the redistribution wirings (122b/122a),
wherein the redistribution wiring layer (120) further includes:
a protective layer (124b, para [0026]) provided on the at least one insulating layer (124a) and having an opening (para [0026] Insulating material 124b is patterned to form openings over portions of the second portion 122b of the RDL 120) that exposes at least a portion of a first redistribution wiring (122b) among the redistribution wirings (122b/122a); and
a bonding pad (122c, para [0013] called under-bump metallization structure or UBM) provided on the at least a portion of the first redistribution wiring (122b) that is exposed by the opening of the protective layer (124b), and
wherein an outer connection member (126, para [0013] conductive material) of outer connection members (126, see Fig. 2) is arranged on the bonding pad (122c) and covers a portion of the first redistribution wiring (122b) that is exposed by the bonding pad (122c).
Tsai et al. is explicitly silent of disclosing wherein, the bonding pad that is exposed by the opening of the protective layer and spaced apart from an inner wall of the opening of the protective layer.
Chen et al. teaches wherein (Fig. 13), the under bump metallurgy (UBM) pad (216: 216b, para [0021]) that is exposed by the opening (220a, para [0026]) of the protective layer (220) and spaced apart from an inner wall of the opening (220a) of the protective layer (220).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Chen et al., and modify the opening in the isolation coating with wider opening of Tsai et al., that exposed the UBM layers, in order to mitigate the heat generation in the redistribution layers and UBM pads, thus more reliable the bonding structure.
Examiner’s Note
14. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
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16. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812