DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 25-28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The limitations of claims 25-28 constitute new matter, not supported by the originally filed specification. For example, there is no teaching or suggestion directed to the thickness direction and the reduced thickness.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Demizu et al. (US6787797B2) in view of Nakamura et al. (JP2014110411A) and further in view of Sato et al. (JP2002110592A).
Re claim 1, Demizu et al. teach a method of processing a semiconductor wafer comprising forming an oxide film on the backside of the wafer, partially removing the oxide film by etching with HF, and polishing the wafer backside (claim 13, Example 1).
Demizu et al. teach the invention substantially as claimed with the exception of etching to remove particles adhering to the film, together with the film. Nakamura et al. teach a semiconductor manufacturing method comprising etching the wafer to remove the layer as well as embedded coarse particles (page 3, last paragraph). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have modified the method of Demizu et al. to include an etching step which removes both the layer and embedded particles, as taught by Nakamura et al., as a conventional step during the manufacturing process of a semiconductor wafer.
Demizu et al. in view of Nakamura teach the invention substantially as claimed with the exception of suppressing damage to the substrate surface during polishing. Sato et al. teach polishing a wafer, comprising a polishing apparatus which can easily flatten a rough surface of a film while suppressing damage during polishing (abstract). Sato et al. teach polishing to remove preferentially rough projections on the film and to flatten the polishing surface of the film while suppressing damage to a layer below the polished film. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the modified method of Demizu et al. to include polishing the film and removing the rough projections, as taught by Sato et al., for purposes of performing the same function of suppressing the damage to underlying layers of the substrate during the polishing. Additionally, the concept of suppressing damage to the substrate during polishing is well known in the art, as evidenced by JP2004146798A, JP2010153781A, West et al. US2014/0124900A1).
7. Claim(s) 2-4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Demizu et al. (US6787797B2) in view of Nakamura et al. (JP2014110411A) and Sato et al. (JP2002110592A) and further in view of Ookawa et al. (TW202113962A; machine translation).
Re claim 2, Demizu et al. in view of Nakamura et al. and Sato et al. fail to teach cleaning with a brush after polishing. Ookawa et al. teach a method of processing semiconductor devices comprising performing various processes in including cutting, slicing, followed by flattening the surface by etching and polishing. Fig. 7(e) teaches that the back surfaces are scrubbed and cleaned after polishing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the modified method of Demizu et al. to include a brush after polishing, as taught by Ookawa et al., for purposes of cleaning the substrate surface to remove residual contaminants. Re claim 3, refer to page 7 of the machine translation of Ookawa et al. which teaches supplying cleaning liquid during the polishing process. Re claim 4, Demizu et al. in view of Ookawa et al. do not a spray mist. However, Ookawa et al. teach supplying a cleaning liquid with a nozzle 160, and the skilled artisan would reasonably expect spraying the nozzle would result in a mist on the substrate surface. Additionally, claims 4 and 12 are broadly interpreted as any liquid would read on a cleaning liquid and therefore supplying a liquid after cleaning with a brush, would read on the wet etching of Fig. 7f, wherein the rear surface is being supplied with a liquid after the surface is treated with a brush in Fig. 7e.
8. Claim(s) 7 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Demizu et al. (6787797) in view Nakamura et al. (JP2014110411A) and Sato et al. (JP2002110592A) and further in view of Hisashi (JP2004-071836A).
Demizu et al. in view of Nakamura et al. and Sato et al. teach the invention substantially as claimed with the exception of the silicon oxide or silicon nitride films on a semiconductor substrate. Hisashi et al. teach a method of manufacturing a semiconductor substrate comprising a silicon oxide film deposited on the back surface and further teaches cleaning the back surface of the wafer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include a silicon oxide film, as taught by Hisashi et al., as such films are conventional during the manufacturing of the semiconductor substrate.
9. Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Demizu et al. (6787797) in view Nakamura et al. (JP2014110411A) and Sato et al. (JP2002110592A) and further in view of Mizuno et al. (US2012/0067846A1).
Demizu et al. in view of Nakamura et al. and Sato et al. teach the invention substantially as claimed with the exception of etching by sequentially supplying multiple chemical liquids to the rear surface of the substrate. Mizuno et al. teach a method of processing a substrate comprising treating the rear surface with HF followed by a second processing liquid comprising ammonia/hydrogen peroxide mixture (abstract; Fig. 4, steps S11, S12) to remove a film on the rear surface (paragraph 25). Re claims 16-18, refer to paragraph 140 and Fig. 12 of Mizuno et al. for example. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to have modified the modified method of Demizu et al. to include supplying multiple chemicals sequentially, as taught by Mizuno et al. for purposes of effectively etching the substrate surface.
Response to Arguments
10. The rejection of the claims, under 112, second paragraph is withdrawn in view of the newly amended limitations.
11. The rejections of the claims as being unpatentable over Demizu et al. in view of Mizuno et al. are withdrawn in view of the newly amended limitations of which are taught by Nakamura et al. and Sato et al. for the reasons recited above. The limitations of etching to remove film and embedded particles, as well as suppressing damage during polishing, are taught by the prior art, for the reasons recited above. The examiner does not consider the new limitations as patentable subject matter for the reasons of record. The secondary reference of Mizuno et al. is relied upon to teach the conventional step of applying multiple liquids during etching.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sharidan Carrillo whose telephone number is (571)272-1297. The examiner can normally be reached M-F, 7:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Barr can be reached on 571-272-1414. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Sharidan Carrillo
Primary Examiner
Art Unit 1711
/Sharidan Carrillo/Primary Examiner, Art Unit 1711 bsc
Prosecution Insights