DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (USPN 11,538,432).
With respect to claim 1, Jung et al. discloses, in Figs. 1-3 and 6, a buffer circuit (Fig. 1, further details disclosed in Figs. 2-3 and 6) that generates an output voltage (VOUT) based on an input voltage (VIN), comprising:
an input stage (110, details disclosed in Fig. 2) configured to provide a differential current (I1-I4) to a load stage (120, details disclosed in Fig. 3) based on a difference between the input voltage and the output voltage (I1-I4 are generated according to the difference between VIN and VOUT);
the load stage (120) configured to apply gate voltages (output of 120, see VOP and VON of Fig. 3) to output transistors (MP8 and MN8 of Fig. 3) of an output stage (130 of Figs. 1 and 3) based on the differential current (VOP and VON are generated based on I1-I4);
the output stage configured to regulate the output voltage based on the gate voltages applied to the output transistors (VOUT generated/regulated from/by 130 based on VON and VON); and
a slew rate compensator (102, details disclosed in Fig. 6) configured to provide or receive a first slew rate compensation current (one of the currents supplied/sunk to/from the PG node by TN3-1 and TP6 of Fig. 6 and supplied/sunk to/from the NG node by TN3 and TP6-1 of Fig. 6) and a second slew rate compensation current (other one of the currents supplied/sunk to/from the PG node by TN3-1 and TP6 of Fig. 6 and supplied/sunk to/from the NG node by TN3 and TP6-1 of Fig. 6) to or from the load stage (at the PG/P4 and NG/P8 nodes of 120 of Fig. 3),
wherein the slew rate compensator comprises a first slew rate compensation circuit including first to third slew rate compensation PMOS transistors only (TP6-1, TP6 and TP5. Note no explicit details are of the first slew rate compensator are required by claim 1 except that it includes only three PMOS transistors that have a current mirror structure. TP5, TP6 and TP6-1 is such a three PMOS transistor current mirror device), each of the second (one of TP6-1 and TP6) and third (other one of TP6-1 and TP6) slew rate compensation PMOS transistors having a current mirror structure (mirroring current from TP5) based on the first slew rate compensation PMOS transistor (TP5), and a second slew rate compensation circuit including first to third slew rate compensation NMOS transistors only (TN3-1, TN3 and TN2. Note no explicit details are of the second slew rate compensator are required by claim 1 except that it includes only three NMOS transistors that have a current mirror structure. TN3-1, TN3 and TN2 is such a three NMOS transistor current mirror device), each of the second (one of TN3-1 and TN3) and third (other one of TN3-1 and TN3) slew rate compensation NMOS transistors having a current mirror structure (TN3-1 and TN3 mirror the current of TN2) based on the first slew rate compensation NMOS transistor (TN2),
wherein the first slew rate compensation circuit is configured to provide the first slew rate compensation current (one of Im6 and Im5, i.e., current provided/sourced to one of PG and NG) and the second slew rate compensation current (other one of Im6 and Im5, i.e., current provided/sourced to other one of PG and NG) to the load stage (to one of the PG and NG nodes of the load), and the second slew rate compensation circuit is configured to receive the first slew rate compensation current (one of Im4 and Im6, i.e., one of the currents received/sunk from one of PG and NG) and the second slew rate compensation current (other one of Im4 and Im6, i.e., other one of the currents received/sunk from one of PG and NG) from the load stage (from one of the PG and NG nodes of the load), and
wherein the second slew rate compensation PMOS or NMOS transistor provides or receives a current mirror-based compensation current to or from the load (the PMOS transistors provide, i.e., source, a current to the load and the NMOS transistors receive, i.e., sink, a current from the load).
With respect to claim 2, the buffer circuit of claim 1, wherein the slew rate compensator comprises a comparator configured to compare the difference between the input voltage and the output voltage and go into an ON or OFF state based on the difference between the input voltage and the output voltage (32 of Fig. 6, see Col. 11 line 10 to Col. 12 line 19).
With respect to claim 3, the buffer circuit of claim 2, wherein the first slew rate compensation PMOS transistor (TP5) is connected to the comparator (via, TN4 and TN6) and is configured to allow a first slew rate compensation reference current to flow therein (current flowing through T5 and TN6, e.g., mirrored version of Id2), and
wherein the third slew rate compensation PMOS transistor has a parallel structure with the second slew rate compensation PMOS transistor ( TP6 and TP6-1 are parallel connected).
With respect to claim 4, the buffer circuit of claim 3, wherein the first slew rate compensation PMOS transistor has a gate connected to the comparator (gate of TP5 connected to 32 via the current mirroring of TN4 and TN6), a drain connected to the comparator in common with the gate (drain and gate of TP5 are connected in common), and a source connected to a power supply voltage (source connected to VDD);
wherein the second slew rate compensation PMOS transistor (one of TP6 and TP6-1) has a gate connected to the comparator in common with the gate of the first slew rate compensation PMOS transistor (gates TP6 and TP6-1 connected to gate of TP5), a drain connected to a third node (one of the PG and NG nodes) of a third output terminal of a second differential mirror circuit of the load stage (output of one of the current mirrors of 122A and 124A of Fig. 3), and a source connected to the power supply voltage (VDD), and
wherein the third slew rate compensation PMOS transistor (other one of TP6 and TP6-1) has a gate connected to the comparator in common with the gate of the first slew rate compensation PMOS transistor (gates TP6 and TP6-1 connected to gate of TP5), a drain connected to a first node (other one of PG and NG nodes) of a first output terminal of a first differential mirror circuit of the load stage (other one of the current mirrors of 122A and 124A of Fig. 3), and a source connected to the power supply voltage (VDD).
With respect to claim 5, the buffer circuit of claim 3, wherein the first slew rate compensation circuit mirrors the first slew rate compensation reference current flowing in a branch to which the first slew rate compensation PMOS transistor is connected into a branch to which the third slew rate compensation PMOS transistor is connected to provide the first slew rate compensation current to the load stage (one of TP6 and TP6-1 mirrors the current flowing through the TP5 and TN6 branch to provide the first slew rate compensation current to one of PG and NG of the load stage), and
wherein the first slew rate compensation circuit mirrors the first slew rate compensation reference current flowing in the branch to which the first slew rate compensation PMOS transistor is connected into a branch to which the second slew rate compensation PMOS transistor is connected to provide the second slew rate compensation current to the load stage (the other one of TP6 and TP6-1 mirrors the current flowing through the TP5 and TN6 branch to provide the second slew rate compensation current to the other one of PG and NG of the load stage).
With respect to claim 6, the buffer circuit of claim 2, wherein the first slew rate compensation NMOS transistor (TN2) is connected to the comparator (via the current mirroring of TP3 and TP4) and is configured to allow a second slew rate compensation reference current to flow therein (current flowing through the TP4 and TN2 branch, e.g., mirrored version of Id1), and
wherein the third slew rate compensation NMOS transistor has a parallel structure with the second slew rate compensation NMOS transistor (TN3 and TN3-1 are connected in parallel).
With respect to claim 7, the buffer circuit of claim 6, wherein the first slew rate compensation NMOS transistor has a gate connected to the comparator (gate of TN2 connected to 32 via the current mirroring of TP3 and TP4), a drain connected to the comparator in common with the gate (drain and gate of TN2 are connected in common), and a source connected to a ground voltage (VSS),
wherein the second slew rate compensation NMOS transistor (one of TN3 and TN3-1) has a gate connected to the comparator in common with the gate of the first slew rate compensation NMOS transistor (gates of TN3 and TN3-1 are connected to the gate of TN2), a drain connected to a first node (one of the PG and NG nodes) of a first output terminal of a first differential mirror circuit of the load stage (one of the current mirrors of 122A and 124A of Fig. 3), and a source connected to the ground voltage (VSS), and
wherein the third slew rate compensation NMOS transistor (other one of TN3 and TN3-1) has a gate connected to the comparator in common with the gate of the first slew rate compensation NMOS transistor (gates of TN3 and TN3-1 are connected to the gate of TN2), a drain connected to a third node (other one of PG and NG nodes) of a third output terminal of a second differential mirror circuit of the load stage (other one of the current mirrors of 122A and 124A of Fig. 3), and a source connected to the ground voltage (VSS).
With respect to claim 8, the buffer circuit of claim 6, wherein the second slew rate compensation circuit mirrors the second slew rate compensation reference current flowing in a branch to which the first slew rate compensation NMOS transistor is connected into a branch to which the second slew rate compensation NMOS transistor is connected to receive the first slew rate compensation current from the load stage (the current through the TP4 and TN2 branch is mirrored by one of TN3 and TN3-1 to receive/sink the first slew rate compensation current from one of the PG and NG nodes), and
wherein the second slew rate compensation circuit mirrors the second slew rate compensation reference current flowing in the branch to which the first slew rate compensation NMOS transistor is connected into a branch to which the third slew rate compensation NMOS transistor is connected to receive the second slew rate compensation current from the load stage (the current through the TP4 and TN2 branch is mirrored by the other one of TN3 and TN3-1 to receive/sink the second slew rate compensation current from the other one of the PG and NG nodes).
With respect to claim 18, a method of controlling a buffer circuit as defined in claim 1, the method comprising:
comparing the input voltage and the output voltage (32 compares VIN and VOUT);
providing or receiving first and second slew rate compensation currents using transistors configured in a current mirror structure (current mirror of TN2, TN3 and TN3-1 and/or TP5, TP6 and TP6-1 providing the first and second slew rate compensation currents), wherein the second slew rate compensation PMOS or NMOS transistor mirrors a reference current of the first slew rate compensation PMOS or NMOS transistor (the second transistor mirrors the first transistor in each of the PMOS and NMOS current mirrors); and
driving the load stage and output stage such that the output voltage follows a transition of the input voltage (the circuit operates as a buffer such that the output voltage follows the input voltage transitions).
With respect to claim 19, the method of claim 18, further comprising:
providing the first and second slew rate compensation currents to the load stage in response to the input voltage exceeding a value obtained by adding the threshold voltage of the MOS transistor to the output voltage (at such a time TN1 of Fig. 6 is active and the first and second slew rate compensation currents are provided to PG and NG via TN3-1 and TN3 of Fig. 6);
switching the first differential mirror circuit to an OFF state so that the first compensation mirror current does not flow (at such a time TN3-1 is actively pulling PG node low such that 122A is off and not sourcing current to PG), and switching the second differential mirror circuit to an ON state so that the second compensation mirror current flows based on the first slew rate compensation current and the second slew rate compensation current (at such at time 124A is active and TN3 aides in the pulling down of current at the NG and PG nodes and, as discussed above, TN3-1 aides in the pulling down of the PG node);
decreasing the gate voltages of the first and second output transistors based on the first compensation mirror current and the second compensation mirror current (when TN3-1 and TN3 are active to pull current down from PG and NG the gate voltages of VOP and VON will decrease); and
allowing the output voltage to increase and follow a rising transition of the input voltage in response to a decrease in the gate voltages of the first and second output transistors (when VOP decreases MP8 becomes active to source NOUT/VOUT thus causing VOUT to increase. Furthermore, when VON decreases MN8 is off such that it does not pull current away from NOUT, thus allowing VOUT to increase).
With respect to claim 20, the method of claim 18, further comprising:
receiving the first slew rate compensation current and the second slew rate compensation current from the load stage when the input voltage becomes lower than a value obtained by subtracting the threshold voltage of the MOS transistor from the output voltage (when the difference between VIN and VOUT is lower than the threshold of TP1 of Fig. 6 TP6 and TP6-1 become active to source the currents to the NG and PG nodes);
switching the first differential mirror circuit to an ON state so that the first compensation mirror current flows (at such at time TP6 is active to source current to the PG node and aiding the ON current mirror of 124A of Fig. 3 in sourcing current to the PG node), and switching the second differential mirror circuit to an OFF state so that the second compensation mirror current does not flow (at such a time TP6-1 is active to source current to 124A such that 124A is off, i.e., not sinking current) based on the first slew rate compensation current and the second slew rate compensation current (the currents providing by the circuit of Fig. 6 control the current mirror outputs);
increasing the gate voltages of the first and second output transistors based on the first compensation mirror current and the second compensation mirror current (when TP6 and TP6-1 source more current to the PG and NG nodes the voltages VOP and VON increase); and
allowing the output voltage to decrease and follow a falling transition of the input voltage in response to an increase in the gate voltages of the first and second output transistors (when VON increases MN8 turns on to pull down the NOUT node. Thus, VOUT decreases and follows a falling transition of VIN. Additionally, when VOP increases MP8 turns off such that MP8 no longer sources NOUT thus adding in the decrease of VOUT).
Allowable Subject Matter
Claims 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-16 are allowed.
With respect to claim 9, there is no cited art that disclose, the buffer circuit of claim 2, wherein the comparator comprises:
a first comparator comprising an NMOS transistor having a gate connected to the input voltage, a drain connected to the first slew rate compensation circuit, and a source connected to the output voltage; and
a second comparator comprising a PMOS transistor having a gate connected to the input voltage, a drain connected to the second slew rate compensation circuit, and a source connected to the output voltage, and
wherein the NMOS transistor of the first comparator has a body connected to the output voltage in common with the sources of the first comparator and the second comparator” (Examiner’s emphasis).
No cited art discloses the first comparator comprising an NMOS transistor connected as claimed and having a drain connected to the first slew rate compensation circuit connected and operative as recited in claim 1 (from which claims 2 and 9 depend). And a PMOS transistor connected as claimed and having a drain connected to the second slew rate compensation circuit connected and operative as recited in claim 1.
For instance Jung et al. fails to disclose the drain of TN1 being connected to TP5, TP6 and TP6-1 and fails to disclose the drain of TP1 being connected to TN2, TN3 and TN3-1. Furthermore, assuming, arguendo, that the teachings of Jung et al. and Kim (USPN 11,711,059) were combined. It is noted that the first and second slew rate compensation circuits (230 and 250 of Fig. 3) of Kim (USPN 11,711,059) include an additional bias transistor (MP1; MN1). Thus, assuming arguendo, that one would add an additional current mirror transistor to MP2 and MP21 and an additional current mirror transistor to MN21 and MN2 to achieve the first through third current mirroring PMOS and NMOS transistors of the first and second slew rate compensation circuits of claim 1. The compensation current generating circuits would include more than three transistors due to the inclusion of bias transistors MP1 and MN1. It is further noted that Fig. 6 of Jung et al. (USPN 11,538,432) also includes two bias transistor TP2 and TN5 that are connected similar to MP1 and MN1 of Kim. Thus, assuming, arguendo, that the teachings of Kim and Jung et al. were combined the combined circuitry would still include more than three transistors in the first and second slew rate compensation circuits due to the included bias transistors. Thus, the above combination fails to disclose all of the recited limitations of claim 9 and further including the first and second slew rate compensation circuits including only three PMOS transistors and only three NMOS transistors respectively. Further note that the bias transistors control the amount of current through the current mirror and thus are not external/separate to the current mirror.
With respect to claims 10-14, the buffer circuit of claim 1, wherein the load stage comprises:
a first differential mirror circuit having a first current mirror structure and a cascode structure and configured to mirror the differential current generated by the difference between the input voltage and the output voltage and the first slew rate compensation current;
a second differential mirror circuit having a second current mirror structure and a cascode structure and configured to mirror the differential current and the second slew rate compensation current; and
a third bias circuit and a fourth bias circuit connected between the first differential mirror circuit and the second differential mirror circuit to control an operation in a static state and an amplification operation of the first differential mirror circuit and the second differential mirror circuit” (Examiner’s emphasis).
No cited art discloses the first and second differential current mirrors that mirror the differential current and the first and second slew rate compensation currents, respectively, as connected and operative as recited in claim 10 in combination with the wherein the slew rate compensator connected and operative as recited in claim 1 that includes “a first slew rate compensation circuit including first to third slew rate compensation PMOS transistors only, each of the second and third slew rate compensation PMOS transistors having a current mirror structure on the first slew rate compensation PMOS transistor, and a second slew rate compensation circuit including first to third slew rate compensation NMOS transistors only, each of the second and third slew rate compensation NMOS transistors having a current mirror structure based on the first slew rate compensation NMOS transistor”.
For instance, the first and second compensation circuits of Fig. 6 of Jung et al. (i.e., the circuit that includes only three PMOS and only three NMOS transistors connected as claimed) provides the first and second compensation currents to the output nodes (PG and NG) the current mirrors (122A; 112B). Thus, the current mirrors do not mirror the first and second and second compensation currents, since the above currents are not mirrored and/or provided to the inputs of the current mirror. Furthermore, the first and second slew rate compensation circuits (230 and 250 of Fig. 3) of Kim (USPN 11,711,059) include an additional bias transistor (MP1; MN1). Thus, assuming arguendo, that one would add an additional current mirror transistor to MP2 and MP21 and an additional current mirror transistor to MN21 and MN2 to achieve the first through third current mirroring PMOS and NMOS transistors of the first and second slew rate compensation circuits of claim 1. The compensation current generating circuits would include more than three transistors due to the inclusion of bias transistors MP1 and MN1. It is further noted that Fig. 6 of Jung et al. (USPN 11,538,432) also includes two bias transistor TP2 and TN5 that are connected similar to MP1 and MN1 of Kim. Thus, assuming, arguendo, that the teachings of Kim and Jung et al. were combined the combined circuitry would still include more than three transistors in the first and second slew rate compensation circuits due to the included bias transistors. Thus, the above combination fails to disclose all of the recited limitations of claim 10 and further including the first and second slew rate compensation circuits including only three PMOS transistors and only three NMOS transistors respectively. Further note that the bias transistors control the amount of current through the current mirror and thus are not external/separate to the current mirror.
Claims 15-16 are allowed for similar reasons as claim 9.
Response to Arguments
Applicant's arguments filed 3/2/2026 have been fully considered but they are not persuasive.
The argument that Jung et al. fails to disclose “wherein the slew rate compensator comprising a first slew rate compensation circuit including first to third slew rate compensation PMOS transistors only, ... and a second slew rate compensation circuit including first to third slew rate compensation NMOS transistors only" is not persuasive. As can be seen, TP6-1, TP6 and TP5 includes only PMOS transistors and TN3-1, TN3 and TN2 includes only NMOS transistors. Thus, Jung et al. meets the above recited claim limitations.
The argument that “Jung discloses a single slew rate compensation circuit that includes both PMOS and NMOS transistors operating together as part of one compensation block” is not persuasive, since such an argument is false. As can be seen TN3-1, TN3 and TN2 operate based on the Id1 current that is independent of the Id2 current which TP6-1, TP6 and TP5 operate with. The above circuitry is a single distinct circuit, but rather two distinct current sinking (i.e., the NMOS current sinks TN3-1, TN3 and TN2) and current sourcing (i.e., the PMOS current sources TP6-1, TP6 and TP5). Assuming, arguendo, that TN3-1, TN3 and TN2 and TP6-1, TP6 and TP5 of Jung et al. are not distinct circuits. Then Applicant’s first and second compensation current sources of 420 and 430 of Fig. 4A would could not be considered distinct circuits either, since they are cooperative with each other under the control of comparator 410 of Fig. 4A. As can be seen the first and second compensation circuitry of Jung et al. operates in similar manner as 420 and 430 of Applicant’s invention. Furthermore, the operation of Jung et al. meets the claimed limitations. Moreover, it is noted that Applicant merely alleges that the PMOS and NMOS transistors operate “together as part of one compensation block” and fails to provide any reasoning as to why one may not consider the PMOS and NMOS transistors as separate and how Jung et al. is different from the claimed invention.
The argument that “Jung does not disclose or suggest separating the slew rate compensator into two distinct compensation circuits, one composed only of PMOS transistors and the other composed only of NMOS transistors, as expressly required by claim 1” is not persuasive. This is because Jung et al. explicitly discloses two distinct compensation current circuit. The first being a compensation current source (i.e., the PMOS current sources TP6-1, TP6 and TP5) and the second being a compensation current sink (TN3-1, TN3 and TN2). As can be seen such devices are separate and distinct. Thus, Applicant’s arguments are not persuasive.
The argument that in “Jung, PMOS and NMOS devices are intermixed within the same compensation circuit and operate cooperatively, rather than being structurally segregated into independent PMOS-only and NMOS-only circuits” is not pervasive for similar reasons discussed above. For instance, Jung et al. explicitly discloses two distinct compensation current circuit. The first being a compensation current source (i.e., the PMOS current sources TP6-1, TP6 and TP5) and the second being a compensation current sink (TN3-1, TN3 and TN2). It can be seen that such devices are separate and distinct. Again it is noted that 420 of Fig. 4A of Applicant’s invention is “intermixed” with 430 of Applicant’s invention via comparator circuit 410. It is noted that the preamble uses the transitional phrase “comprising” which does not limit any additional circuitry being connected within the claimed circuit. As can be seen one may consider TP6-1, TP6 and TP5 only as the first compensation current circuit and TN3-1, TN3 and TN2 only as the second compensation current circuit. Wherein the additional circuitry of Fig. 6 is not interpreted as part of the “compensation current” circuitry since it is only the transistors TP6-1, TP6 with TP5 and TN3-1, TN3 with TN2 that are responsible for directly providing the compensation currents to/from the load. Again, it is noted that the “comprising” transitional phrase allows for additional unclaimed elements.
Moreover, claim 2 of the instant invention requires the possibility for the “slew rate compensator” to include additional transistors that are not part of the “first to third slew rate compensation PMOS transistors only” and the “first to third slew rate compensation NMOS transistors only” since, according to claim 2, the “slew rate compensator” further comprises a “comparator” (i.e., 410 of Fig. 4A). Therefore, the additional transistors may be included in the slew rate compensator. One may consider 32 and TP4, PT2, TP3, TN4, TN5 and TN6 of Fig. 6 of Jung et al. as “the comparator” circuit, since Id1 and Id2, and the current mirrored version of Id1 and I2 from TP4 and TN6, are generated according to the comparison result VIN and VOUT by the comparator. Thus, in such a interpretation there is no other compensation “first to third slew rate compensation PMOS transistors” and the “first to third slew rate compensation NMOS transistors” other than TP6-1, TP6 with T5 and TN3-1, TN3 with TN2 of Jung et al. Therefore, Jung et al. meets the claimed limitations for multiple reasons.
The argument that Jung et al. fails to disclose "each of the second and third slew rate compensation PMOS (or NMOS) transistors having a current mirror structure based on the first slew rate compensation PMOS (or NMOS) transistor" is not persuasive. This is because the above allegation is false. As can be seen, TN2, TN3 and TN3-1 constitute an NMOS current mirror and TP5, TP6 and TP6-1 constitute a PMOS current mirror (see Col. 13 lines 40-43 and Col. 13 line 65 to Col. 14 line 3). Thus the circuitry produces “mirroring currents” and must therefore be have “a current mirror structure”.
The argument that “Jung does not disclose a three-transistor mirror structure in which two parallel mirror branches simultaneously mirror a single reference transistor within the same compensation circuit” not persuasive since it is false. As can be seen TP6-1, TP6 and TP5 are connected in parallel. Furthermore, TP6-1 and TP6 simultaneously mirror the single reference transistor TP5 (i.e., mirror Id2 from TP5 as provided from the comparator/TN6). Similarly, TN3-1, TN3 and TN2 are connected in parallel. Furthermore, TN3-1 and TN3 simultaneously mirror the single reference transistor TN2 (i.e., mirror Id1 from TN2 as provided from the comparator/TP4).
The argument “Jung instead describes current mirrors in general terms, without teaching or suggesting the specific configuration in which two separate compensation currents are generated by mirroring a single reference transistor” is not persuasive. As can be seen above Jung discloses two distinct current mirror circuits operating as required.
The argument Jung et al. fails to disclose "wherein the first slew rate compensation circuit is configured to provide the first and second slew rate compensation currents to the load stage, and the second slew rate compensation circuit is configured to receive the first and second slew rate compensation currents from the load stage” is not persuasive. This is because the currents provided by/sourced from TP6-1 and TP6 are sourced/provided to the load at nodes PG and NG and the currents provided to/sunk by TN3-1 and TN3 are sunk from/received from nodes PG and NG of the load.
The arguments that claim 1 “expressly requires that both slew rate compensation currents are provided to or received from the load stage, such that slew rate enhancement is performed indirectly through the load stage” and that “Jung, by contrast, injects at least one compensation current directly into an output node or an output transistor gate, rather than exclusively interfacing with the load stage” are not persuasive. All that is required by the claims is that the compensation currents are provided to/from the load stage. Jung et al. meets these requirements by sourcing and sinking currents to/from both of the PG and NG nodes of the load. Furthermore, at least part of the the current sourced/sunk at PG by the compensation current circuits will flow through/come from at least one of 122A and MP7 with MN7 of the load and at least part of the current sourced/sunk at NG by the compensation current circuits will flow through/come from at least one of 124A and MP7 with MN7 of the load. Thus, the circuit of Jung et al. meets the claim limitations.
The argument that “because Jung routes compensation current directly to the output stage, Jung does not disclose a configuration in which both compensation currents are exchanged solely with the load stage as required by claim 1” is not persuasive, since the claims do not require that “both compensation currents are exchanged solely with the load stage” (Examiner’s emphasis). Rather the claims merely require that the compensation currents are provided to/from the load circuit. As discussed above, the compensation currents are at least partially provided to/from the load circuitry. Thus, the circuit of Jung et al. meets the recited claim limitations.
The argument that Jung et al. fails to disclose "wherein the second slew rate compensation PMOS or NMOS transistor provides or receives a current mirror-based compensation current to or from the load stage” is not persuasive, since it is false. TP6-1 provides a current, Im6, to node NG of the load, TP6 provides a current, Im5, to node PG of the load, TN3-1 receives a current, Im4, from node PG of the load, and Im3 receives a current, Im3, from node NG of the load. Thus, Jung et al. operates as claimed.
The statement that in “Jung, the primary compensation current is generated directly by the comparator transistor and is not a mirrored current when applied to the output node” is incorrect. The comparator (32; or alternatively 32 with TP3, TP2, TP4, TN4, TN5 and TN6) generates at least two currents (Id1 or Id1 mirrored by TP4 in the alternative interpretation; and Id2 or Id2 mirrored by TN6 in the alternative interpretation) that are not “generated directly by the comparator”, but rather output by being mirrored by TN2, TN3 with TN3-1 and TP5, TP6 with TP6-1, respectively.
Examiner agrees with the statement that claim 1 “requires that the compensation current exchanged with the load stage is current-mirror-derived, not a direct comparator output current”. Additionally, as discussed above, it can be seen that the output of the comparator is current mirror driven by TN2, TN3 with TN3-1 and TP5, TP6 with TP6-1, respectively.
Thus the argument that “Jung therefore fails to disclose providing or receiving a current mirror-based compensation current to or from the load stage, as expressly recited in claim 1” is not persuasive, since it can be seen that Jung does, in fact, provide for such current mirror-based compensation current to/from the load.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2836
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