DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 9 March 2026 is acknowledged.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9 March 2026.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted On 1 September 2023, 1 October 2024, and 1 April 2026 have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 6-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh et al (US 20220359563 A1, hereinafter “Noh”).
Regarding Claim 1 - Noh discloses a three-dimensional memory device, comprising: alternating stacks of insulating layers (ILDa and ILDb [0093] and Fig. 5C) and electrically conductive layers (ELa and ELb [0093] and Fig. 5C), wherein each of the alternating stacks laterally extends along a first horizontal direction (D1 [0047] and Fig. 5C), and the alternating stacks are laterally spaced apart from each other along a second horizontal direction (D2 [0056] and Fig. 5A) by lateral isolation trenches (SH [0121] and Fig. 5A); arrays of memory openings, wherein each array of memory openings vertically extends through a respective one of the alternating stacks (CH [0070] and Fig. 5B); arrays of memory opening fill structures located within the arrays of memory openings (VS1 [0068] and Fig. 5C), wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements (DSP [0073] and Fig. 8) and a vertical semiconductor channel (VSP [0073] and Fig. 8); and composite lateral isolation trench fill structures located between a respective neighboring pair of the alternating stacks (3230 [0044] and Fig. 3, and SP [0087] and Fig. 5A), wherein each of the composite lateral isolation trench fill structures comprises a dielectric pillar structure (SPa [0089] ad Fig. 5A) which vertically extends at least from first horizontal plane including a bottom of the alternating stacks to a second horizontal plane including a top of the alternating stacks (Fig. 5C).
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Regarding Claim 2 - Noh further discloses the three-dimensional memory device of Claim 1, wherein the dielectric pillar structure comprises an elongated dielectric pillar structure that comprises: a middle portion laterally extending along the first horizontal direction with a uniform width along the second horizontal direction; and a pair of end portions having a respective vertically-straight and laterally-concave sidewall (SPa has uniform width in center and rounded ends [0096] and Fig. 5A).
Regarding Claim 6 - Noh further discloses the three-dimensional memory device of Claim 2, wherein each of the elongated dielectric pillar structures is in contact with a respective pair of laterally-elongated tubular insulating spacers each having an undulating lateral extent along the second horizontal direction as a function of a lateral distance along the first horizontal direction (Each dielectric pillar SPa away from the last in a row in the regions where ELa and ELb exist has a pair of laterally-extending insulating spacers of the combination of SPa and SPb on either side with undulating lateral extent in direction D2, Fig. 5A).
Regarding Claim 7 - Noh further discloses the three-dimensional memory device of Claim 1, wherein each of the alternating stacks has a respective stepped surface that underlies and contacts a respective stepped dielectric material portion (Steps of ELa&b and ILDa&b are under 130 [0076] and Fig. 5C).
Regarding Claim 8 - Noh further discloses the three-dimensional memory device of Claim 7, wherein the composite lateral isolation trench fill structures comprise: first composite lateral isolation trench fill structures that are not in direct contact with any of the stepped dielectric material portions (SP in CAR [0047] and Fig. 5A); and second composite lateral isolation trench fill structures that contact a respective one of the stepped dielectric material portions (SP in CCR [0047] and Fig. 5A).
Regarding Claim 9 - Noh further discloses the three-dimensional memory device of Claim 8, wherein: each of the first composite lateral isolation trench fill structures comprises a respective pair of first source contact via structures having a first maximum lateral width along the second horizontal direction (Wm [0100] and Fig. 6); and each of the second composite lateral isolation trench fill structures comprises a respective additional first source contact via structure having the first maximum lateral width along the second horizontal direction and a second source contact via structure having a second maximum lateral width along the second horizontal direction that is greater than the first maximum lateral width (Wm can vary, for example 110-210nm [0100] and Fig. 6).
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Regarding Claim 10 - Noh further discloses the three-dimensional memory device of Claim 7, wherein a contiguous set of the stepped surfaces continuously extends at least from a bottommost electrically conductive layer within one of the alternating stacks to a topmost electrically conductive layer within said one of the alternating stacks (Horizontal and vertical surfaces of stepped layers ELa&b and ILDa&b form a contiguous set from bottommost ELa to topmost ELb [0076] and Fig. 5C).
Regarding Claim 11 - Noh further discloses the three-dimensional memory device of Claim 7, further comprising layer contact via structures vertically extending through a respective one of the stepped dielectric material portions and contacting a respective electrically conductive layer within the alternating stacks (CCP [0081] and Fig. 5C).
Regarding Claim 12 - Noh further discloses the three-dimensional memory device of Claim 7, further comprising dielectric support pillar structures vertically extending through a respective one of the stepped dielectric material portions (VS2 passes through 130 in CCR Figs. 5A and 5B), wherein the dielectric support pillar structures and the dielectric pillar structures comprise a same dielectric fill material (130 contains silicon oxide, silicon nitride, silicon oxynitride an/or low-k dielectric [0077], and VS2 contains silicon oxide and silicon nitride or silicon oxynitride [0075] and [0106]).
Regarding Claim 13 - Noh further discloses the three-dimensional memory device of Claim 7, wherein a subset of the dielectric pillar structures is in direct contact with a respective pair of the alternating stacks and a respective pair of the stepped dielectric material portions (SP in direct contact on both sides in direction D2 with ELa&b/ILDa&b and 130, Figs. 5A and 5C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al (US 20220359563 A1, hereinafter “Noh”), in view of Lee (KR 20150116995 A, hereinafter “Lee”).
Regarding Claim 3 - Noh discloses all the limitations of Claim 2.
Noh further discloses each of the composite lateral isolation trench fill structures further comprises a pair of lengthwise sidewalls that generally extend along the first horizontal direction and having a laterally-undulating width along the second horizontal direction that undulates along the first horizontal direction (Periodic narrowing DP in width Wm in direction D2 along length of structure SP in direction D1, Noh [0101] and Fig.6).
Noh fails to disclose each of the composite lateral isolation trench fill structures further comprises at least one source contact via structure.
However, Lee discloses each of the composite lateral isolation trench fill structures further comprises at least one source contact via structure (175, Lee [0081] and Fig. 13).
Lee discloses a similar three-dimensional memory structure to Noh. Lee teaches placing source contact vias in isolation fill structures for the benefit of electrically connect the substrate (Lee [0081-0082]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Noh and Lee to place source contact vias in isolation fill structures for the benefit of electrically connecting the substrate to a known potential.
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Regarding Claim 4 - Noh modified by Lee discloses all the limitations of Claim 3.
The combination of Noh and Lee further discloses the three-dimensional memory device of Claim 3, wherein each of the at least one source contact via structure is laterally surrounded by a laterally-elongated tubular insulating spacer having an undulating lateral extent along the second horizontal direction as a function of a lateral distance along the first horizontal direction (Periodic narrowing DP in width Wm in direction D2 along length of structure SP in direction D1, Noh [0101] and Fig. 6).
Regarding Claim 5 - Noh modified by Lee discloses all the limitations of Claim 3.
The combination of Noh and Lee further discloses each of the at least one source contact via structure comprises a respective bottom surface contacting a respective row of semiconductor pedestals (110, Lee [0031] and Fig. 13); and each of the memory opening fill structures further comprises a respective pedestal channel portion having a same material composition as the semiconductor pedestals (130, Lee [0031] and Fig. 13).
Lee discloses a similar three-dimensional memory structure to Noh. Lee teaches forming semiconductor pedestals under channel structures for the benefit of connecting source potential to the end of the channel (Lee [0040] and Fig. 13). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Noh and Lee to form pedestal channel portions under channel structures for the benefit of connecting source potential to the end of the channel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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