DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 30 April 2026 has been entered.
Response to Amendment
Acknowledgment is made of applicant’s Amendment, filed 30 April 2026. The changes and remarks disclosed therein have been considered.
No claims have been cancelled, claims 13-16 are newly added by Amendment. Therefore, claims 1-16 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (JP2023-037895 Japan 03/10/2023).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “a fifth transistor whose first terminal is connected to the first node and the second node; and a sixth transistor whose first terminal is connected to the third node and the fourth node” as recited in claims 13-16, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-11, 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2014/0145773 A1) in view of Arimoto et al (JP 2005353274 A hereinafter “Arimoto”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Hashimoto, for example in Figs. 1-29, discloses a data latch circuit (see for example in Figs. 28-29 related in Figs. 1-27), comprising:
a first circuit (see for example in Fig. 17 related in Figs. 1-16, 18-29) in which a first transistor (e.g., 12; in Fig. 17 related in Figs. 1-16, 18-29) with a first conductivity type (e.g., P-type; in Fig. 17 related in Figs. 1-16, 18-29) and a second transistor (e.g., 15; in Fig. 17 related in Figs. 1-16, 18-29) with a second conductivity type (e.g., N-type; in Fig. 17 related in Figs. 1-16, 18-29) that differs from the first conductivity type are connected in series (see for example in Fig. 17 related in Figs. 1-16, 18-29) and which is configured to store a first logical value (implied that is inverter’s function; in Fig. 17 related in Figs. 1-16, 18-29); and
a second circuit (see for example in Fig. 17 related in Figs. 1-16, 18-29) in which a third transistor (e.g., 13; in Fig. 17 related in Figs. 1-16, 18-29) with the first conductivity type (e.g., P-type; in Fig. 17 related in Figs. 1-16, 18-29) and a fourth transistor (e.g., 16; in Fig. 17 related in Figs. 1-16, 18-29) with the second conductivity type (e.g., N-type; in Fig. 17 related in Figs. 1-16, 18-29) are connected in series and which is configured to store a second logical value (implied that is inverter’s function; in Fig. 17 related in Figs. 1-16, 18-29) being an inversion of the first logical value (see for example in Fig. 17 related in Figs. 1-16, 18-29), wherein
one of a first voltage (e.g., VDD; in Fig. 15 related in Figs. 1-14, 16-29) and a second voltage (e.g., RE/WR; in Fig. 15 related in Figs. 1-14, 16-29) that differs from the first voltage can be applied to back gates of the first transistor and the third transistor (e.g., VBG(P); in Fig. 15 related in Figs. 1-14, 16-29) and a third voltage can be applied to sources of the first transistor and the third transistor (e.g., VDD; in Fig. 15 related in Figs. 1-14, 16-29),
when data is transferred from the first circuit and the second circuit, the second voltage is applied to the back gate of the first transistor and the back gate of the third transistor (see for example in Fig. 17 related in Figs. 1-16, 18-29), and wherein the data latch circuit further comprises
a first node that is connected to a drain of the first transistor and a drain of the second transistor (e.g., a node is connected to between transistor 12 and transistor 15; in Fig. 15 related in Figs. 1-14, 16-29), and is connected to a second node that is connected to a gate of the third transistor and a gate of the fourth transistor (e.g., a node that is connected to transistor 13 and transistor 16; n Fig. 15 related in Figs. 1-14, 16-29 ), and
a third node that is connected to a drain of the third transistor and a drain of the fourth transistor (e.g., a node that is connected to transistor 13 and transistor 16; in Fig. 15 related in Figs. 1-14, 16-29), and is connected to a fourth node that is connected to a gate of the first transistor and a gate of the second transistor (e.g., a node that is connected to transistor 13 and transistor 15; in Fig. 15 related in Figs. 1-14, 16-29).
However, Hashimoto is silent with regard to the second voltage is different from the third voltage.
In the same field of endeavor, Arimoto, for example in Figs. 1-27, discloses the second voltage is different from the third voltage (e.g., Vcc1 is different to Vcc, and different to Vpp1 or Vpp2; in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hashimoto such as semiconductor integrated circuit having back-gate voltage control circuit (see for example in Figs. 1-29 of Hashimoto) by incorporating the teaching of Arimoto such as semiconductor circuit (see for example in Figs. 1-27 of Arimoto), for the purpose of controlling the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels (Arimoto disclosed).
The structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
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Regarding claim 2, the above Hashimoto/Arimoto, combination discloses wherein when the data is stored in the first circuit and the second circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27, as discussed above), the first voltage is applied to the back gates of the first transistor and the third transistor and the third voltage can be applied to the sources of the first transistor and the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27, as discussed above), and when the data is transferred from the first circuit and the second circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27, as discussed above), the second voltage, which is higher than the first voltage, is applied to the back gates of the first transistor and the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27, as discussed above), the third voltage is applied to the sources of the first transistor and the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27, as discussed above), and the data is based on the first logical value and the second logical value (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27, as discussed above). Also, the structure in of the prior art (Hashimoto and Teraoka) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 3, Hashimoto, for example in Figs. 1-29, discloses a data latch circuit (see for example in Figs. 28-29 related in Figs. 1-27), comprising:
a first circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29) in which a first transistor (e.g., 12; in Fig. 15 related in Figs. 1-14, 16-29) with a first conductivity type (e.g., P-type; in Fig. 15 related in Figs. 1-14, 16-29) and a second transistor (e.g., 15; in Fig. 15 related in Figs. 1-14, 16-29) with a second conductivity type (e.g., N-type; in Fig. 15 related in Figs. 1-14, 16-29) that differs from the first conductivity type are connected in series (see for example in Fig. 15 related in Figs. 1-14, 16-29) and which is configured to store a first logical value (implied that is inverter’s function; in Fig. 15 related in Figs. 1-14, 16-29); and
a second circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29) in which a third transistor (e.g., 13; in Fig. 15 related in Figs. 1-14, 16-29) with the first conductivity type (e.g., P-type; in Fig. 15 related in Figs. 1-14, 16-29) and a fourth transistor (e.g., 16; in Fig. 15 related in Figs. 1-14, 16-29) with the second conductivity type (e.g., N-type; in Fig. 15 related in Figs. 1-14, 16-29) are connected in series (see for example in Fig. 15 related in Figs. 1-14, 16-29) and which is configured to store a second logical value (implied that is inverter’s function; in Fig. 15 related in Figs. 1-14, 16-29) being an inversion of the first logical value (see for example in Fig. 15 related in Figs. 1-14, 16-29), wherein
one of a first voltage (e.g., WR/RE; in Fig. 15 related in Figs. 1-14, 16-29) and a second voltage (e.g., RE/WR; in Fig. 15 related in Figs. 1-14, 16-29) that differs from the first voltage can be applied to sources of the first transistor and the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29) and a third voltage can be applied to back gates of the first transistor and the third transistor (e.g., VBG(P); in Fig. 15 related in Figs. 1-14, 16-29),
when data is transferred from the first circuit and the second circuit, the second voltage is applied to the source of the first transistor and the source of the third transistor (in Fig. 15 related in Figs. 1-14, 16-29), and wherein the data latch circuit further comprises
a first node that is connected to a drain of the first transistor and a drain of the second transistor (e.g., a node is connected to between transistor 12 and transistor 15; in Fig. 15 related in Figs. 1-14, 16-29), and is connected to a second node that is connected to a gate of the third transistor and a gate of the fourth transistor (e.g., a node that is connected to transistor 13 and transistor 16; n Fig. 15 related in Figs. 1-14, 16-29 ), and
a third node that is connected to a drain of the third transistor and a drain of the fourth transistor (e.g., a node that is connected to transistor 13 and transistor 16; in Fig. 15 related in Figs. 1-14, 16-29), and is connected to a fourth node that is connected to a gate of the first transistor and a gate of the second transistor (e.g., a node that is connected to transistor 13 and transistor 15; in Fig. 15 related in Figs. 1-14, 16-29).
However, Hashimoto is silent with regard to the second voltage is different from the third voltage.
In the same field of endeavor, Arimoto, for example in Figs. 1-27, discloses the second voltage is different from the third voltage (e.g., Vcc1 is different to Vcc, and different to Vpp1 or Vpp2; in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hashimoto such as semiconductor integrated circuit having back-gate voltage control circuit (see for example in Figs. 1-29 of Hashimoto) by incorporating the teaching of Arimoto such as semiconductor circuit (see for example in Figs. 1-27 of Arimoto), for the purpose of controlling the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels (Arimoto disclosed).
The structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 4, the above Hashimoto/Arimoto, combination discloses wherein when the data is stored in the first circuit and the second circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), the first voltage is applied to the sources of the first transistor and the third transistor and the third voltage is applied to the back gates of the first transistor and the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), and when the data is transferred from the first circuit and the second circuit, a second voltage, which is lower than the first voltage, is applied to the sources of the first transistor and the third transistor (e.g., WR; in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), and the third voltage is applied to the back gates of the first transistor and the third transistor (e.g., VBG(P); in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Hashimoto/Arimoto, combination discloses wherein the first voltage and the third voltage have a same potential (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 6, Hashimoto, for example in Figs. 1-29, discloses a semiconductor device, comprising: the data latch circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29, as discussed above); and a power supply circuit configured to apply the first voltage or the second voltage to the back gates or the sources of the first transistor and the third transistor of the data latch circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29) including a first circuit in which a first transistor with a first conductivity type and a second transistor with a second conductivity type that differs from the first conductivity type are connected in series and which is configured to store a first logical value (see for example in Fig. 15 related in Figs. 1-14, 16-29); and a second circuit in which a third transistor with the first conductivity type and a fourth transistor with the second conductivity type are connected in series and which is configured to store a second logical value being an inversion of the first logical value (see for example in Fig. 15 related in Figs. 1-14, 16-29), wherein one of a first voltage and a second voltage that differs from the first voltage can be applied to back gates of the first transistor and the third transistor and a third voltage can be applied to sources of the first transistor and the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29), and when data is transferred from the first circuit and the second circuit, the second voltage is applied to the back gate of the first transistor and the back gate of the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29); and a power supply circuit configured to apply the first voltage or the second voltage to the back gates or the sources of the first transistor and the third transistor of the data latch circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29), and wherein the data latch circuit further comprises
a first node that is connected to a drain of the first transistor and a drain of the second transistor (e.g., a node is connected to between transistor 12 and transistor 15; in Fig. 15 related in Figs. 1-14, 16-29), and is connected to a second node that is connected to a gate of the third transistor and a gate of the fourth transistor (e.g., a node that is connected to transistor 13 and transistor 16; n Fig. 15 related in Figs. 1-14, 16-29 ), and
a third node that is connected to a drain of the third transistor and a drain of the fourth transistor (e.g., a node that is connected to transistor 13 and transistor 16; in Fig. 15 related in Figs. 1-14, 16-29), and is connected to a fourth node that is connected to a gate of the first transistor and a gate of the second transistor (e.g., a node that is connected to transistor 13 and transistor 15; in Fig. 15 related in Figs. 1-14, 16-29).
However, Hashimoto is silent with regard to the second voltage is different from the third voltage.
In the same field of endeavor, Arimoto, for example in Figs. 1-27, discloses the second voltage is different from the third voltage (e.g., Vcc1 is different to Vcc, and different to Vpp1 or Vpp2; in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hashimoto such as semiconductor integrated circuit having back-gate voltage control circuit (see for example in Figs. 1-29 of Hashimoto) by incorporating the teaching of Arimoto such as semiconductor circuit (see for example in Figs. 1-27 of Arimoto), for the purpose of controlling the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels (Arimoto disclosed).
The structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 7, the above Hashimoto/Arimoto, combination discloses wherein the power supply circuit is configured to apply the first voltage or the second voltage to the back gates of the first transistor and the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), the power supply circuit is configured to apply the first voltage to the back gates of the first transistor and the third transistor when the data is stored in the first circuit and the second circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), and the power supply circuit is configured to apply the second voltage to the back gates of the first transistor and the third transistor when the data is transferred from the first circuit and the second circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 8, the above Hashimoto/Arimoto, combination discloses wherein the power supply circuit is configured to apply the first voltage or the second voltage to the sources of the first transistor and the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), the power supply circuit is configured to apply the first voltage to the sources of the first transistor and the third transistor when the data is stored in the first circuit and the second circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), and the power supply circuit is configured to apply the second voltage to the sources of the first transistor and the third transistor when the data is transferred from the first circuit and the second circuit (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 9, the above Hashimoto/Arimoto, combination discloses comprising the data latch circuit in plurality, wherein the power supply circuit is configured to apply power to the data latch circuit in plurality see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 10, the above Hashimoto/Arimoto, combination discloses further comprising the power supply circuit in plurality, and the data latch circuit in plurality (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), wherein a first power supply circuit among the power supply circuit in plurality is configured to apply power to a first data latch circuit among the data latch circuit in plurality (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), and a second power supply circuit among the power supply circuit in plurality is configured to apply power to a second data latch circuit among the data latch circuit in plurality (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 11, the above Hashimoto/Arimoto, combination discloses further comprising the power supply circuit in plurality, wherein a first power supply circuit among the power supply circuit in plurality is configured to apply power to the first transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above), and a second power supply circuit among the power supply circuit in plurality is configured to apply power to the third transistor (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 13, the above Hashimoto/Arimoto, combination discloses further comprising: a fifth transistor whose first terminal is connected to the first node and the second node; and a sixth transistor whose first terminal is connected to the third node and the fourth node (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 14, the above Hashimoto/Arimoto, combination discloses further comprising: a fifth transistor whose first terminal is connected to the first node and the second node; and a sixth transistor whose first terminal is connected to the third node and the fourth node (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Regarding claim 15, the above Hashimoto/Arimoto, combination discloses further comprising: a fifth transistor whose first terminal is connected to the first node and the second node; and a sixth transistor whose first terminal is connected to the third node and the fourth node (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto and also see in Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto, as discussed above). Also, the structure in of the prior art (Hashimoto and Arimoto) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Claims 12, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2014/0145773 A1) in view of Arimoto et al (JP 2005353274 A hereinafter “Arimoto”) and further in view of Kamata et al (US 10,720,220 B2 hereinafter “Kamata”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 12, the above Hashimoto/Arimoto, combination discloses the claimed invention as discussed above. However, the above Hashimoto/Teraoka is silent with regard to a semiconductor storage device, comprising: a memory cell transistor; a bit line connected to the memory cell transistor; a sense amplifier unit which is connected to the bit line.
In the same field of endeavor, Kamata, for example in Figs. 1-24, discloses a semiconductor storage device, comprising: a memory cell transistor; a bit line connected to the memory cell transistor; a sense amplifier unit which is connected to the bit line (see for example in Figs. 1-2, 5 related in Figs. 3-4, 6-24).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hashimoto such as semiconductor integrated circuit having back-gate voltage control circuit (see for example in Figs. 1-29 of Hashimoto) and the teaching of Arimoto such as semiconductor circuit (see for example in Figs. 1-27 of Teraoka) by incorporating the teaching of Kamata such as sense amplifier having a sense transistor to which different voltage are applied during sensing and after sensing to correct a variation of the threshold voltage of the sense transistor (see for example in Figs. 1-24 of Kamata), for the purpose of controlling the control circuit is configured to adjust a voltage applied to a back gate of the sense transistor or a source of the sense transistor to correct a variation of a threshold voltage of the sense transistor (Kamata, see Abstract).
Regarding claim 16, the above Hashimoto/Arimoto/Kamato, combination discloses further comprising: a fifth transistor whose first terminal is connected to the first node and the second node; and a sixth transistor whose first terminal is connected to the third node and the fourth node (see for example in Fig. 15 related in Figs. 1-14, 16-29 of Hashimoto with Figs. 17, 22 related in Figs. 1-16, 18-21, 23-27 of Arimoto and also see in Figs. 1-2, 5 related in Figs. 3-4, 6-24 of Kamato, as discussed above). Also, the structure in of the prior art (Hashimoto, Arimoto and Kamato) is substantially identical to the structure of the claims. MEPE 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MEPE 2114(II).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 II A).
Response to Arguments
Applicant's arguments filed 30 April 2026have been fully considered but are moot because a new ground(s) of rejection is made in view of Arimoto et al (JP 2005353274 A hereinafter “Arimoto”).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 05/11/2026
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