DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on August 22, 2025.
Claims 1, 3-4, 6, 9, 14, 16-18, and 20 are amended. No claims are canceled or added. Claims 1-20 are pending.
Applicant’s amendments to the specification submitted on August 22, 2025 are acknowledged and the objections to the specification are withdrawn.
Response to Arguments
3. Applicant’s arguments, see pages 9-10, filed August 22, 2025, with respect to the objection to the duplication of labels in FIG. 4, have been fully considered but they are not persuasive. Applicant asserts “the duplication of labels or reference numerals in the drawings is permissible under USPTO drawing standards, provided that such duplication does not result in ambiguity.” However, MPEP §608.02(e) states “no single reference character is used for two different parts or for a given part and a modification of such part.”
However, based on ¶ [0048] in the present application, one may understand the reference symbols DT0 and ST0 to refer to a plurality of devices rather than a single device. In this case, using these symbols to reference more than one device in FIG. 4 may not be objectionable. Based on this interpretation and the amendments to the drawing, the objection to the drawings is withdrawn.
4. Applicant’s arguments, see page 10, filed August 22, 2025, with respect to the rejection of claims 3-4, 6, and 9 under 35 USC § 112 have been fully considered and are persuasive.
Examiner agrees the amendments to claim 3-4, 6, and 9 remove the ambiguity associated with “the write time” and therefore the 112(b) rejection is withdrawn.
5. Applicant’s arguments, see pages 11-14, filed August 22, 2025, with respect to the rejections of claims 1-6, 10-14, and 16-20 under 35 USC § 103 have been fully considered and are persuasive.
Regarding independent claims 1, 14, and 18, Applicant asserts Darragh, et al (US 20150186072 A1), hereinafter Darragh, FIG. 17 and paragraphs [0068]-[0069], as cited in the previous Office Action, does satisfy "[controlling] a write time for a next write based on information corresponding to a combination of the measured erase time and the measured write time" as recited in claim 1. Applicant further asserts Kim (US 20220238169 A1) FIGS. 10-11 and paragraphs [0004] and [0080]-[0083], also cited in the previous Office Action, does not remedy the deficiencies of Darragh.
Examiner agrees the specific citations in the previous Office Actions do not clearly identify how Darragh as modified by Kim would satisfy "[controlling] a write time for a next write based on information corresponding to a combination of the measured erase time and the measured write time" as recited in claims 1, 14, and 18. Therefore, the rejection of claims 1-6, 10-14, and 16-20 has been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Steiner, et al (US 8995197 B1), hereinafter Steiner.
6. Applicant’s arguments, see page 14, filed August 22, 2025, with respect to the rejections of claims 7-9 and 15 under 35 USC § 103 have been fully considered and are persuasive.
Regarding claim 7, Applicant asserts Moon (US 20210103406 A1) does not make up for the deficiencies of Darragh and Kim with respect to independent claim 1 upon which claim 7 depends. Examiner agrees and therefore the rejection has been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Steiner.
Regarding claims 8-9 and 15, Applicant asserts Weingarten, et al (US 20120216085 A1) does not make up for the deficiencies of Darragh and Kim with respect to independent claim 1 upon which claims 8-9 depend, and claim 14, upon which claim 15 depends. Examiner agrees and therefore the rejection has been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Steiner.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-2 and 4-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Steiner, et al (US 8995197 B1), hereinafter Steiner.
Regarding independent claim 1, Steiner teaches a memory controller (FIG. 16, 420) comprising:
an interface circuit connectable to a memory (FIG. 16, implied by communication link between controller 420 and memory 460); and
a processor (Col. 15, ll. 22-23) configured to:
measure an erase time required to erase data (Col. 16, ll. 57-60) from the memory via the interface circuit;
measure a write time required to write data to the memory via the interface circuit (Col. 16, ll. 57-60; FIG. 8, tPROG from step 186); and
control a write time for a next write (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time; Col. 3, ll. 16-19 teaches the adapted programming parameters are subject to a programming duration threshold) based on information corresponding to a combination of the measured erase time and the measured write time (Col. 16, ll. 55-56; Col. 16, l. 65 – Col. 17, l.24; note Tprog and Terase in equation of Col. 16, ll. 65-67).
Regarding claim 2, Steiner teaches the limitations of claim 1.
Steiner further teaches the memory includes a plurality of blocks (FIG. 16, 440(1..4); Col. 27, l. 55), and
wherein the erase time is measured for each block of the memory (FIG. 6, steps 150 and 152).
Regarding claim 4, Steiner teaches the limitations of claim 1.
Steiner further teaches the processor is configured to control the write time for the next write by adjusting a write parameter, the write parameter being related to the write time for the next write (Col. 2, ll. 56-62 teaches “evaluated” (l. 41) program parameters include number of program pulses, voltage steps, etc.).
Regarding claim 5, Steiner teaches the limitations of claim 4.
Steiner further teaches the write parameter includes a parameter related to a write voltage or a verification voltage when writing data to the memory (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, program verify levels, etc.).
Regarding claim 6, Steiner teaches the limitations of claim 1.
Steiner further teaches the processor is configured to control the write time for the next write (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time; Col. 3, ll. 16-19 teaches the adapted programming parameters are subject to a programming duration threshold) based on the measured erase time and the write time required to write data to the memory (Col. 16, ll. 55-56; Col. 16, l. 65 – Col. 17, l.24; note Tprog and Terase in equation of Col. 16, ll. 65-67), and based on additional information different from the erase time and the write time required to write data to the memory (Col. 16, ll. 57-67 teaches the score based on previous programming that is used to adapt parameters for future programming includes BER).
Regarding claim 7, Steiner teaches the limitations of claim 6.
Steiner further teaches the additional information includes information that affects a change of the erase time or the write time (e.g., the score calculation of Col. 16, ll. 57-67 is used to optimize erase and write parameters (FIG. 5; Col. 17, ll. 26-32), which affect a change in erase and/or write time (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time; Col. 3, ll. 16-19 teaches the adapted programming parameters are subject to a programming duration threshold)).
Regarding claim 8, Steiner teaches the limitations of claim 1.
Steiner further teaches the processor is configured to specify a first numerical value range to which the erase time belongs among a plurality of first numerical value ranges, specify a second numerical value range to which the write time belongs among a plurality of second numerical value ranges, and control the write time based on the specified first numerical value range and specified second numerical value range (Col. 20, l. 51 – Col. 21, l. 3; FIG. 9, define/receive N program/erase cycles (202) for each range C..Ci, (204), and update the program or erase parameters for the current cycle range (208) until C belongs to the next range (212), wherein erase cycles represent the “first” range and program cycles represent the “second” range; Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time; Col. 3, ll. 16-19 teaches the adapted programming parameters are subject to a programming duration threshold).
Regarding claim 9, Steiner teaches the limitations of claim 8.
Steiner further teaches the processor is further configured to control the write time for the next write by adjusting a write parameter, the write parameter being related to the write time for the next write, based on the specified first numerical value range and specified second numerical value range (Col. 20, l. 51 – Col. 21, l. 3; FIG. 9, define/receive N program/erase cycles (202) for each range C..Ci, (204), and update the program or erase parameters for the current cycle range (208) until C belongs to the next range (212)).
Regarding claim 10, Steiner teaches the limitations of claim 1.
Steiner further teaches the processor is configured to shorten the write time, by a shortened amount, from the measured write time based on the measured erase time and measured write time (Col. 4, ll. 6-10 teaches “selecting a set of evaluated parameters that once applied results in … a lower programming duration at low wear levels”; note Tprog and Terase in equation of Col. 16, ll. 65-67).
Regarding claim 11, Steiner teaches the limitations of claim 10.
Steiner further teaches the processor is further configured to change the shortened amount of the write time based on the measured erase time and measured write time (Col. 16, ll. 55-56; Col. 16, l. 65 – Col. 17, l.24; note Tprog and Terase in equation of Col. 16, ll. 65-67. The score calculation of Col. 16, ll. 57-67 is used to optimize erase and write parameters (FIG. 5; Col. 17, ll. 26-32), which affect a change in erase and/or write time (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time)).
Regarding claim 12, Steiner teaches the limitations of claim 1.
Steiner further teaches the processor is configured to extend the write time, by an extended amount, from the measured write time based on the measured erase time and measured write time (Col. 3, ll. 16-19 teaches the method may include ignoring sets of programming parameters that once applied result in an average duration of programming operations that exceeds a programming duration threshold, which indicates the program time can be “extended” by the programming parameters; note Tprog and Terase in equation of Col. 16, ll. 65-67).
Regarding claim 13, Steiner teaches the limitations of claim 12.
Steiner further teaches the processor is further configured to change the extended amount of the write time based on the measured erase time and measured write time (Col. 16, ll. 55-56; Col. 16, l. 65 – Col. 17, l.24; note Tprog and Terase in equation of Col. 16, ll. 65-67. The score calculation of Col. 16, ll. 57-67 is used to optimize erase and write parameters (FIG. 5; Col. 17, ll. 26-32), which affect a change in erase and/or write time (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time)).
Regarding independent claim 14, Steiner teaches a control method of a memory (e.g., FIGS. 5, 7), the method comprising:
measuring an erase time required to erase data from the memory (Col. 16, ll. 57-60);
measuring a write time required to write data to the memory (Col. 16, ll. 57-60; FIG. 8, tPROG from step 186); and
controlling a write time for a next write (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time; Col. 3, ll. 16-19 teaches the adapted programming parameters are subject to a programming duration threshold) based on information corresponding to a combination of the measured erase time and the measured write time (Col. 16, ll. 55-56; Col. 16, l. 65 – Col. 17, l.24; note Tprog and Terase in equation of Col. 16, ll. 65-67).
Regarding claim 15, Steiner teaches the limitations of claim 14.
Steiner further teaches specifying a first numerical value range to which the erase time belongs among a plurality of first numerical value ranges, specifying a second numerical value range to which the write time belongs among a plurality of second numerical value ranges, and controlling the write time based on the specified first numerical value range and specified second numerical value range (Col. 20, l. 51 – Col. 21, l. 3; FIG. 9, define/receive N program/erase cycles(202) for each range C..Ci, (204), and update the program or erase parameters for the current cycle range (208) until C belongs to the next range (212), wherein erase cycles represent the “first” range and program cycles represent the “second” range).
Regarding claim 16, Steiner teaches the limitations of claim 14.
Steiner further teaches shortening the write time from the measured write time based on the measured erase time and measured write time (Col. 16, ll. 55-56; Col. 16, l. 65 – Col. 17, l.24; note Tprog and Terase in equation of Col. 16, ll. 65-67. The score calculation of Col. 16, ll. 57-67 is used to optimize erase and write parameters (FIG. 5; Col. 17, ll. 26-32), which affect a change in erase and/or write time (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time)).
Regarding claim 17, Steiner teaches the limitations of claim 14.
Steiner further teaches extending the write time from the measured write time based on the measured erase time and measured write time (Col. 3, ll. 16-19 teaches the method may include ignoring sets of programming parameters that once applied result in an average duration of programming operations that exceeds a programming duration threshold, which indicates the program time can be “extended” by the programming parameters; note Tprog and Terase in equation of Col. 16, ll. 65-67).
Regarding independent claim 18, Steiner teaches a memory system (FIG. 16) comprising:
a memory (FIG. 16, 460) including a plurality of memory cells (FIG. 16, within memory pages 430); and
a processor (Col. 15, ll. 22-23) configured to:
measure an erase time required to erase data from a part of the memory cells (Col. 16, ll. 57-60),
measure a write time required to write data to a part of the memory cells (Col. 16, ll. 57-60; FIG. 8, tPROG from step 186), and
control a write time for a next write (Col. 2, ll. 56-62 teaches program parameters include number of program pulses, voltage steps, etc., which determine write time; Col. 3, ll. 16-19 teaches the adapted programming parameters are subject to a programming duration threshold) based on information corresponding to a combination of the measured erase time and the measured write time (Col. 16, ll. 55-56; Col. 16, l. 65 – Col. 17, l.24; note Tprog and Terase in equation of Col. 16, ll. 65-67).
Regarding claim 19, Steiner teaches the limitations of claim 18.
Steiner further teaches the memory includes a plurality of blocks (FIG. 16, 440 (1..4); Col. 27, l. 55), and
wherein the erase time is measured for each block of the memory (FIG. 6, steps 150 and 152).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claims 3 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Steiner, et al (US 8995197 B1), hereinafter Steiner, in view of Kim (US 20220238169 A1), hereinafter Kim.
Regarding claim 3, Steiner teaches the limitations of claim 1.
Steiner further teaches the memory includes a plurality of word lines (FIG. 16, pages 430, which are defined by word lines (or rows – see Col. 22, ll. 53-57)).
Steiner does not teach the write time required to write data to the memory is measured for each word line group including word lines among the plurality of word lines of the memory.
Kim teaches the write time required to write data to the memory is measured for each word line group including word lines among the plurality of word lines of the memory (FIG. 12; ¶ [0004-0006] teach programming times are confirmed and adjusted/set on a per-word-line basis).
Regarding claim 20, Steiner teaches the limitations of claim 18.
Steiner further teaches the memory further includes a plurality of word lines (FIG. 16, pages 430, which are defined by word lines (or rows – see Col. 22, ll. 53-57).
Steiner does not teach the write time is measured for each word line group including word lines among the plurality of word lines of the memory.
Kim teaches the write time required to write data to the memory is measured for each word line group including word lines among the plurality of word lines of the memory (FIG. 12; ¶ [0004-0006] teach programming times are confirmed and adjusted/set on a per-word-line basis).
Regarding claims 3 and 20, It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kim into the method of Steiner to include confirming and adjusting/setting write time on a per-word-line basis. The ordinary artisan would have been motivated to modify Steiner in the above manner for the purpose of ensuring the variation width of the writing speed is smaller than a reference value (Abstract; ¶ [0004]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/HUAN HOANG/ Primary Examiner, Art Unit 2827