DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I (semiconductor device) reflected in claims 1-11 in the reply filed on 01/12/2026 is acknowledged. Claim 12 is withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6-8 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by TAKAYA; Hidefumi (US 20250294836 A1, hereinafter Takaya‘836).
Regarding independent claim 1, Takaya‘836 teaches, “A semiconductor device (fig. 1-8; ¶ [0020] - ¶ [0048]), comprising:
a first electrode (22, see annotated fig. 8 in next page);
a first semiconductor region (12) located on the first electrode (22), the first semiconductor region (12) being of a first conductivity type (n+);
a second semiconductor region (144) located on the first semiconductor region (12),
the second semiconductor region (144) being of the first conductivity type (n-),
a first-conductivity-type impurity concentration (n-) of the second semiconductor region (144) being less than a first-conductivity-type impurity concentration (n+) of the first semiconductor region (12),
the second semiconductor region (144/14, ‘n-type drift region’) including a first part (see annotation) and a second part (see annotation), the second part being located on a portion of the first part;
a third semiconductor region (146) located on another portion of the first part, the third semiconductor region (146) being of a second conductivity type (p), a second-conductivity-type impurity concentration (p) of the third semiconductor region (146, ‘a p-type column high-concentration layer’, ¶ [0025]) being greater than the first-conductivity-type impurity concentration (n-) in the second semiconductor region (144, ‘n-type column low-concentration layers 144’, ¶ [0024]);
a fourth semiconductor region (142) separated from the third semiconductor region (146) in a second direction (X) with the second part interposed, the second direction (X) being perpendicular to a first direction (Z), the first direction being from the first electrode (22) toward the first semiconductor region (12), the fourth semiconductor region (142) being of the first conductivity type (n),
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a first-conductivity-type impurity concentration (n) of the fourth semiconductor region (142) being greater than the first-conductivity-type impurity concentration (n-) of the second semiconductor region (144);
a fifth semiconductor region (16) located on the third semiconductor region (146), the fifth semiconductor region (16) being of the second conductivity type (p);
a sixth semiconductor region (18) located on the fifth semiconductor region (16), the sixth semiconductor region (18) being separated from the second part with a portion of the fifth semiconductor region (16) interposed, the sixth semiconductor region (18) being of the first conductivity type (n+);
a gate electrode (32) facing the portion of the fifth semiconductor region (16) via a gate insulating layer (34); and
a second electrode (24) located on the fifth and sixth semiconductor regions (16 and 18), the second electrode (24) being electrically connected with the fifth and sixth semiconductor regions (16 and 18, by ‘p+-type body contact region 19’)”.
Regarding claim 4, Takaya‘836 further teaches, “The device according to claim 1, wherein an upper portion of the fourth semiconductor region (142, fig. 8) contacts the gate insulating layer (34)”.
Regarding claim 6, Takaya‘836 further teaches, “The device according to claim 1, wherein
a plurality of the third semiconductor regions (146) is provided,
a plurality of the fourth semiconductor regions (142) is provided,
a plurality of the second parts (see annotation in fig. 8) is provided,
the plurality of third semiconductor regions (146) and the plurality of fourth semiconductor regions (142) are alternately arranged along the second direction (X), and
each of the plurality of second parts is positioned between the third semiconductor region (146) and the fourth semiconductor region (142)”.
Regarding claim 7, Takaya‘836 further teaches, “The device according to claim 6, wherein a first-conductivity-type impurity concentration (n-, ‘n-type column low-concentration layer 144’, ¶ [0026]) of the second part (144) is less than the second-conductivity-type impurity concentration (p) in the third semiconductor region (146, ‘a p-type column high-concentration layer 146’, ¶ [0025]) and less than the first-conductivity-type impurity concentration in the fourth semiconductor region (142, n)”.
Regarding claim 8, Takaya‘836 further teaches, “The device according to claim 7, wherein the first-conductivity-type impurity concentration of the second part is equal to the first-conductivity-type impurity concentration of the first part (both first part and second part are part of same layer 14/144/drift layer)”.
Regarding claim 10, Takaya‘836 further teaches, “The device according to claim 6, wherein a length along the second direction (X) of the third semiconductor region (146) is less than a distance between two mutually-adjacent third semiconductor regions (146) among the plurality of third semiconductor regions (146)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Takaya‘836 as applied to claim 1 as above, and further in view of NARITA; Syunki et al. (US 20230275122 A1, Narita‘122).
Regarding claim 2, Takaya‘836 teaches all the limitations described in claim 1.
But Takaya‘836 is silent upon the provision of wherein a length between the fourth semiconductor region and the first semiconductor region is less than a length between the third semiconductor region and the first semiconductor region.
However, Narita‘122 teaches a similar trench gate MOSFET (fig. 3), wherein a length between the fourth semiconductor region (31, n pillar) and the first semiconductor region (1/41) is less than a length between the third semiconductor region (32b) and the first semiconductor region (1/41).
Takaya‘836 and Narita‘122 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takaya‘836 with the features of Narita‘122 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Takaya‘836 and Narita‘122 to include shorter P-columns than the n-columns in the active region according to the teachings of Narita‘122 with a motivation of avoiding the instance of avalanche breakdown by controlling the breakdown voltage of the active region. See Narita‘122, ¶ [0041].
Regarding claim 3, Takaya‘836 modified with Narita‘122 further teaches, “The device according to claim 2, wherein the length between the fourth semiconductor region (31, n pillar, fig. 3, Narita‘122) and the first semiconductor region (1/41) is less than a length along the first direction (Z) between a lower end of the fourth semiconductor region (31) and a lower end of the third semiconductor region (23b)”.
Regarding claim 11, Takaya‘836 modified with Narita‘122 further teaches, “The device according to claim 1, wherein a length between the fourth semiconductor region (31, n pillar, fig. 3, Narita‘122) and the first electrode (16) is less than a length between the third semiconductor region (23b) and the first electrode (16)”.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Takaya‘836 as applied to claim 1 as above, and further in view of Willmeroth et al. (US 20140231912 A1, hereinafter Willmeroth‘912).
Regarding claim 5, Takaya‘836 teaches all the limitations described in claim 1.
But Takaya‘836 is silent upon the provision of wherein, wherein
the sixth semiconductor region is arranged with a portion of the second or fourth semiconductor region in the second direction,
the portion of the fifth semiconductor region is positioned between the sixth semiconductor region and the portion of the second or fourth semiconductor region, and
the gate insulating layer is located on the portion of the fifth semiconductor region, the sixth semiconductor region, and the portion of the second or fourth semiconductor region.
However, Willmeroth‘912 teaches a MOSFET device
the sixth semiconductor region (110, fig. 6A) is arranged with a portion of the second or fourth semiconductor region (121) in the second direction (horizontal direction),
the portion of the fifth semiconductor region (115) is positioned between the sixth semiconductor region (110) and the portion of the second or fourth semiconductor region (121), and
the gate insulating layer (205) is located on the portion of the fifth semiconductor region (115), the sixth semiconductor region (110), and the portion of the second or fourth semiconductor region (121).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Takaya‘836 and Willmeroth‘912 to apply the teaching in a planar type MOSFET according to the teachings of Willmeroth‘912 with a motivation of achieving improved avalanche ruggedness as described by Willmeroth‘912, ¶ [0002].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Takaya‘836 as applied to claim 7 as above, and further in view of Tokano et al. (US 20040238844 A1, hereinafter Tokano‘844).
Regarding claim 9, Takaya‘836 teaches all the limitations described in claim 7.
But Takaya‘836 is silent upon the provision of wherein the first-conductivity-type impurity concentration of the second part is not less than 1x10¹³ atoms/cm³ and not more than 1x10¹⁵ atoms/cm³.
However, Tokano‘844 teaches a similar MOSFET (fig. 3), wherein the first-conductivity-type impurity concentration of the second part (drift layer 2, fig. 1) is not less than 1x10¹³ atoms/cm³ and not more than 1x10¹⁵ atoms/cm³ (¶ [0127]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Takaya‘836 and Tokano‘844 to form the second part/drift region of claimed density according to the teachings of Tokano‘844 with a motivation of lowering ON resistance as taught by Tokano‘844 in ¶ [0006] - ¶ [0027].
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817