DETAILED ACTION
This Office Action is in response to the Amendment filed on May 6, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Chakraborty et al. (US Pub. 2017/0092533 A1) in view of Maes (CN-110993482 A).
In re claim 1, Chakraborty et al. discloses (figs. 1A-1D; [0020]) a method of forming a semiconductor device, the method comprising: forming a first structure (105), wherein forming the first structure comprises: forming a metal layer over a substrate (included within the first structure); forming a dielectric layer (110) over the metal layer;
etching a trench (fig, 1A; 115) in the dielectric layer, wherein the trench extends from a top surface of the dielectric layer down to at least a top surface of the metal layer or deeper; filling the trench with a copper-containing material (fig. 1B, 120); and
selectively depositing a dielectric film (130; fig. 1D; [0020]) on the first structure, the dielectric film overlaying the dielectric layer and not overlaying the copper-containing material. Chakraborty discloses all of the elements of the claims except the dielectric film having a dielectric constant greater than about equal to 7. Maes (CN-110993482-A) discloses (with reference to figures 11A-12A; no actual paragraph numbers; see the translated excerpts below) that a selectively deposited dielectric film (2602) is formed on a dielectric layer (2608) adjacent a copper filled trench (2606). Maes discloses that the dielectric film can be a low-k dielectric film (generally below 4) or high-k dielectric film (generally above 4), depending on the desired result. In this case, a high-k dielectric film would be used to reduce parasitic capacitance. A high-k dielectric film, such as ZrO recited in the reference, has a dielectric constant greater than 7. Even if such is not the case, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the dielectric film having any desired dielectric constant, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the method of forming the semiconductor device of Chakraborty by forming the dielectric film having a dielectric constant greater than 7 to provide an interconnection having reduced parasitic capacitance.
Translated excerpts of Maes:
Example Application
FIG. 11A-11E illustrates a device and device for creating process, in some embodiments, having improved electrical isolation. FIG. 11A illustrates an integrated circuit having portion is configured of the embedded metal component 2606 defines a first surface, the first surface and from the surrounding low-k material 2608 defining second surface flush, planar-like structure shown in FIG. 10A. the metal component comprises further comprises locating the first low-k dielectric material 2608 in Cu TaN barrier material 2610 and first material 2612.
FIG. 11B illustrates a device on the conductive barrier layer 2614 located above the first material after FIG. 11A. In some embodiments, the barrier layer 2614 can be W. Although shown as protruding, but in some embodiments, Cu 2610 line or through hole above the barrier material 2614 can be embedded into the surrounding low-k material 2608 and flush with it.
FIG. 11C illustrates the device after the first surface above the selectively deposited passivation layer 2604 defined by the metal barrier layer 2614 (W) of FIG. 11B, wherein an edge of the first surface is exposed. In some embodiments, the passivation layer 2604 may be an organic material, such as polymer. In some embodiments, sufficient to expose some of the metal surface of the first passivation layer material of etch-back after the selectively deposited passivation layer 2604.
FIG. 11D illustrates the FIG. 11C apparatus on the second surface selectively depositing dielectric layer 2602 so as to overlap with the first metal surface. In some embodiments, dielectric layer 2602 may be a high-k material. In some embodiments, the high-k material may be ZrO2. In some embodiments, the selective dielectric layer 2602 can be a low-k material, such as SiOC, Al2O3 and SiN. In some embodiments, the selective deposition of dielectric material 2602 can serve about through the low k material 2608 for subsequent etching reaches the barrier metal material 2614 exposed by an open trench or via hole etch stop (stop).
FIG. 11E illustrates removing the polymer passivation layer 2604 thus exposed (in this case the barrier material 2614) after the lower metal layer surface of FIG. 11D of the device. selective dielectric 2602 overlap and reduce the subsequent metal components (e.g., upper metal line or through hole) formed on the above short circuit risk. metal defined by the barrier layer 2614 first surface Specifically, the low-k material is deposited over the structure of FIG. 11E, and create an opening and is filled with a metal. to create an opening through the mask and selective low-k etching, and the etching stops on the selective deposition of dielectric (e.g., ZrO2). dielectric selective deposition of 2602 and metal components overlap defined by the barrier layer 2614 (due to passivation, etching back the dielectric deposition and/or terrain during selected conditions) to prevent misalignment. Therefore, the overlap preventing contact with adjacent metal component or the low-k material 2608 for etching is not desired. Note that, the selective deposition of the dielectric material 2602 can stay in the final integrated circuit device, between the ILD layer acts as an etch stop. Although in the metallization process avoids k material of generally high, but the parasitic capacitance is the lowest. the lowest parasitic capacitance is due to high-k material relative to the low-k material has a main guide, the minute parasitic capacitance thickness high-k material so it has due to its function, and the use of such dielectric cap layer with high selectivity relative to high-k material than material selection advantages caused by the more important. Of course, high etching selectivity further can use the low-k material is selectively deposited on the ILD is achieved.
Allowable Subject Matter
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-20 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Edelstein (US Pub. 2014/0353828 A1), He (WO-202320755-A1), (JP-2007533124-A), Parbatani (CN-117981070-A), and Li (CN-114220788-A) disclose various elements of the claims.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2817
