DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges the amendments made to claims 1 and 20. Claims 10-13 have been cancelled. Claims 16 and 17 were previously withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 9 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 9 broadens the claimed interlayer thickness range. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 14-15, and 18-24 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Tanimoto (US 20140175455 A1, hereinafter “Tanimoto”), in view of the following arguments.
Regarding Claim 1 – Tanimoto discloses a Gallium Nitride power transistor ([0053]), comprising: a buffer layer (first nitride semiconductor layer 11 [0054] and Fig. 1); a barrier layer (second nitride semiconductor layer 12 [0054] and annotated Fig. 1) having a top side (TS12) and a bottom side (BS12), the bottom side of the barrier layer facing the buffer layer (Annotated Fig. 1), wherein the bottom side of the barrier layer is disposed on the buffer layer (Annotated Fig. 1); and an interlayer (fourth nitride semiconductor layer 22 [0058] and Fig. 1) interposed between a p-type doped Gallium Nitride layer (third nitride semiconductor layer 24 [0058] and Fig. 1) and a metal gate layer (Annotated Fig. 1), wherein the interlayer is made of a III-V compound semiconductor comprising a combination of at least one group III element with at least one group V element (e.g. AlGaN (a simple written version of AlXGa1-XN) [0058]); wherein the p-type doped Gallium Nitride layer is disposed on the top side of the barrier layer (Fig. 1); and wherein the metal gate layer (gate electrode 21 [0058] and Fig. 1) is configured to electrically connect the p-type doped Gallium Nitride layer via the interlayer to form a rectifying metal-semiconductor junction with the p-type doped Gallium Nitride layer ([0061]), and a content of the group III element within the III-V compound semiconductor is 50 percent (The atomic percent of group III in layer 22 is disclosed as 50% in all cases due to 1:1 ratio between group III and group V components [0094] and [0123-0125] and Figs. 6 and 7. Atomic proportions of AlbGa1-bN show the total of group III (Al + Ga) with a subscript of 1, equalling the portion of group V (N), which also has a subscript of 1).
Tanimoto discloses a thickness of the interlayer is 1-1000 nm ([0067]).
Tanimoto fails to expressly disclose a thickness of the interlayer is 20 nanometers.
However, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05(I). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider selecting an interlayer thickness of 20 nm based on the teaching of Tanimoto.
PNG
media_image1.png
342
477
media_image1.png
Greyscale
PNG
media_image2.png
344
488
media_image2.png
Greyscale
PNG
media_image3.png
376
401
media_image3.png
Greyscale
Regarding Claim 2 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein a gate region of the Gallium Nitride power transistor is formed by a contact region of the p-type doped Gallium Nitride layer with the barrier layer at the top side of the barrier layer ([0060]).
Regarding Claim 3 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the at least one group III element comprises one of the following chemical elements: Aluminum, Gallium, or Indium (e.g. aluminum and gallium [0058]).
Regarding Claim 4 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the at least one group V element comprises one of the following chemical elements: Nitrogen, Phosphorus, Arsenic, or Antimony (e.g. nitrogen [0058]).
Regarding Claim 5 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the metal gate layer is configured to electrically connect the p-type doped Gallium Nitride layer via the interlayer to form a Schottky barrier with the p-type doped Gallium Nitride layer ([0061]).
Regarding Claim 6 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the interlayer comprises Aluminum-Gallium-Nitride ([0058]).
Regarding Claim 9 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein a thickness of the interlayer is within a range of 5 nanometers to 40 nanometers (Tanimoto discloses 1-1000 nm [0067], an overlapping range as explained regarding claim 1).
Regarding Claim 14 – Tanimoto discloses the Gallium Nitride power transistor according to claim 1, wherein the metal gate layer has a top side and a bottom side (TS21 and BS21 in annotated Fig. 1); wherein the interlayer has a top side and a bottom side (TS22 and BS22 in annotated Fig. 1); wherein the p-type doped Gallium Nitride layer has a top side and a bottom side (TS24 and BS24 in annotated Fig. 1); wherein the bottom side of the metal gate layer is disposed on the top side of the interlayer (Annotated Fig. 1); and wherein the bottom side of the interlayer is disposed on the top side of the p-type doped Gallium Nitride layer (Annotated Fig. 1).
Regarding Claim 15 – Tanimoto discloses the Gallium Nitride power transistor according to claim 1, wherein the metal gate layer has a top side and a bottom side; wherein the interlayer has a top side and a bottom side; and wherein the metal gate layer covers at least part of the top side of the interlayer.
Regarding Claim 18 – Tanimoto discloses the Gallium Nitride power transistor according to claim 1, wherein the buffer layer comprises a Gallium Nitride layer or an Aluminum Gallium Nitride layer ([0054]).
Regarding Claim 19 – Tanimoto discloses the Gallium Nitride power transistor according to claim 1, wherein the barrier layer comprises an Aluminum Gallium Nitride layer ([0054]).
Regarding Claim 20 – Tanimoto discloses a metal-semiconductor junction for a Gallium Nitride power transistor, the metal-semiconductor junction comprising: an interlayer (fourth nitride semiconductor layer 22 [0058] and Fig. 1) interposed between a p-type doped Gallium Nitride layer (third nitride semiconductor layer 24 [0058] and Fig. 1) and a metal gate layer (gate electrode 21 [0058] and Fig. 1), wherein the interlayer is made of a III-V compound semiconductor comprising a combination of at least one group III element with at least one group V element (e.g. AlGaN [0058]); and wherein the metal gate layer is configured to electrically connect the p-type doped Gallium Nitride layer via the interlayer to form a rectifying metal-semiconductor junction with the p-type doped Gallium Nitride layer ([0061]); and a content of the group III element within the III-V compound semiconductor is 50 percent (The atomic percent of group III in layer 22 is disclosed as 50% in all cases due to 1:1 ratio between group III and group V components [0094] and [0123-0125] and Figs. 6 and 7. Atomic proportions of AlbGa1-bN mean the total portion of group III (Al + Ga) is 1, compared to an equal portion of group V (N)).
Tanimoto discloses a thickness of the interlayer is 1-1000 nm ([0067]).
Tanimoto fails to expressly disclose a thickness of the interlayer is 20 nanometers.
However, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05(I). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider selecting an interlayer thickness of 20 nm based on the teaching of Tanimoto.
Regarding Claim 21 – Tanimoto further discloses the metal-semiconductor junction according to claim 20, wherein the at least one group III element comprises one of the following chemical elements: Aluminum, Gallium, or Indium (e.g. aluminum and gallium [0058]).
Regarding Claim 22 – Tanimoto further discloses the metal-semiconductor junction according to claim 20, wherein the at least one group V element comprises one of the following chemical elements: Nitrogen, Phosphorus, Arsenic, or Antimony (e.g. nitrogen [0058]).
Regarding Claim 23 – Tanimoto further discloses the metal-semiconductor junction according to claim 20, wherein the metal gate layer is configured to electrically connect the p-type doped Gallium Nitride layer via the interlayer to form a Schottky barrier with the p-type doped Gallium Nitride layer (Electrical connection described in [0061-0062]).
Regarding Claim 24 – Tanimoto further discloses the metal-semiconductor junction according to claim 20, wherein the rectifying metal-semiconductor junction comprises a reverse biased Schottky diode for separating the p-type doped Gallium Nitride layer from the metal gate layer (Schottky depletion layer generated [0061]).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Tanimoto (US 20140175455 A1, hereinafter “Tanimoto”), in view of MPEP 2144.05(I) and 2112(II), and further in view of Sayadi (US 20220199815 A1, hereinafter “Sayadi”).
Regarding Claim 7 – Tanimoto discloses all the limitations of claim 1.
Tanimoto fails to disclose the interlayer comprises Aluminum-Nitride.
However, Sayadi discloses the group III-nitride in the Schottky gate structure (14, Sayadi [0045] and Fig. 1) may include only aluminum and nitrogen (Sayadi [0044]).
Sayadi discloses an analogous compound semiconductor transistor to Tanimoto. Sayadi teaches the group III element(s) forming the nitride semiconductor layers may be selected from aluminum, gallium, indium, and boron, either alone or in combination (Sayadi [0044]). This shows that substituting indium-aluminum-nitride for aluminum-gallium-nitride as the interlayer presents a prima facie case of obviousness, as these are known equivalents in the art. See MPEP 2144.06(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider substituting aluminum-nitride for aluminum-gallium-nitride as the interlayer material, since these are known equivalents in the art.
Regarding Claim 8 – Tanimoto discloses all the limitations of claim 1.
Tanimoto fails to disclose the interlayer comprises Indium-Aluminum-Nitride.
However, Sayadi discloses the group III-nitride in the Schottky gate structure (14, Sayadi [0045] and Fig. 1) may include indium along with aluminum and nitrogen (Sayadi [0044]).
Sayadi discloses an analogous compound semiconductor transistor to Tanimoto. Sayadi teaches the group III element(s) forming the nitride semiconductor layers may be selected from aluminum, gallium, indium, and boron, either alone or in combination (Sayadi [0044]). This shows that substituting indium-aluminum-nitride for aluminum-gallium-nitride as the interlayer presents a prima facie case of obviousness, as these are known equivalents in the art. See MPEP 2144.06(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider substituting indium-aluminum-nitride for aluminum-gallium-nitride as the interlayer material, since these are known equivalents in the art.
PNG
media_image4.png
457
665
media_image4.png
Greyscale
Response to Arguments
Applicant's arguments filed 9 April 2026 have been fully considered but they are not persuasive.
The prior art teaches an overlapping range of interlayer thickness, and a 50-50 ratio for III-V components is also clearly taught, with subscripts carefully used as explained above.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
The arguments of counsel cannot take the place of evidence in the record. In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997). See MPEP 716.01(c).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights