DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 10 December 2025 is acknowledged. Claims 16 and 17 are withdrawn, as reading on an unelected species.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 10-12 are rejected under 35 U.S.C. 112(a), because the specification, while being enabling for 50 percent group III element content of the III-V compound semiconductor, does not reasonably provide enablement for anything below 50 percent. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims. III-V compound semiconductors adhere to a strict stoichiometric ratio of components, obeying the octet rule to satisfy the valence electron requirements of each atom. As commonly known in the industry, the reason an element is chosen from each of group III and group V for III-V compound semiconductor materials is to combine three valence electrons of the group III element with five valence electrons of the group V element to satisfy the octet rule as would be inherent in a single element semiconductor such as silicon or germanium. Therefore, III-V compound semiconductors inherently have a target crystal structure of equal atomic percentage of each component, 50 percent of each type by definition (See, for example, the definition of GaAs at: https://www.webqc.org/compound-GaAs-GaAs.html). This is expressed in written form for each compound without subscripts because the ratio of components is 1:1. For, the twelve III-V compounds in the specification of the claimed invention are AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InN, InP, InAs, and InSb. All of these have a 1:1 ratio between group III and group V elements to satisfy the valence electron requirements of each atom and result in a stable, crystalline semiconductor.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9, 13-15, and 18-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanimoto (US 20140175455 A1, hereinafter “Tanimoto”).
Regarding Claim 1 – Tanimoto discloses a Gallium Nitride power transistor ([0053]), comprising: a buffer layer (first nitride semiconductor layer 11 [0054] and Fig. 1); a barrier layer (second nitride semiconductor layer 12 [0054] and annotated Fig. 1) having a top side (TS12) and a bottom side (BS12), the bottom side of the barrier layer facing the buffer layer (Annotated Fig. 1), wherein the bottom side of the barrier layer is disposed on the buffer layer (Annotated Fig. 1); and an interlayer (fourth nitride semiconductor layer 22 [0058] and Fig. 1) interposed between a p-type doped Gallium Nitride layer (third nitride semiconductor layer 24 [0058] and Fig. 1) and a metal gate layer (Annotated Fig. 1), wherein the interlayer is made of a III-V compound semiconductor comprising a combination of at least one group III element with at least one group V element (e.g. AlGaN [0058]); wherein the p-type doped Gallium Nitride layer is disposed on the top side of the barrier layer (Fig. 1); and wherein the metal gate layer (gate electrode 21 [0058] and Fig. 1) is configured to electrically connect the p-type doped Gallium Nitride layer via the interlayer to form a rectifying metal-semiconductor junction with the p-type doped Gallium Nitride layer ([0061]).
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Regarding Claim 2 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein a gate region of the Gallium Nitride power transistor is formed by a contact region of the p-type doped Gallium Nitride layer with the barrier layer at the top side of the barrier layer ([0060]).
Regarding Claim 3 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the at least one group III element comprises one of the following chemical elements: Aluminum, Gallium, or Indium (e.g. aluminum and gallium [0058]).
Regarding Claim 4 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the at least one group V element comprises one of the following chemical elements: Nitrogen, Phosphorus, Arsenic, or Antimony (e.g. nitrogen [0058]).
Regarding Claim 5 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the metal gate layer is configured to electrically connect the p-type doped Gallium Nitride layer via the interlayer to form a Schottky barrier with the p-type doped Gallium Nitride layer ([0061]).
Regarding Claim 6 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the interlayer comprises Aluminum-Gallium-Nitride ([0058]).
Regarding Claim 7 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein the interlayer comprises Aluminum-Nitride (AlN is simply AlXGa1-XN in which the Ga concentration goes to zero [0058]).
Regarding Claim 9 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein a thickness of the interlayer is within a range of 5 nanometers to 40 nanometers (1-1000 nm [0067]).
Regarding Claim 13 – Tanimoto further discloses the Gallium Nitride power transistor according to claim 1, wherein a thickness of the interlayer is 20 nanometers (1-1000 nm [0067]) and a content of the group III element within the III-V compound semiconductor is 50 percent (The disclosed III-V compositions are all 50-50. See [0124-0125] and Figs. 6 and 7).
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Regarding Claim 14 – Tanimoto discloses the Gallium Nitride power transistor according to claim 1, wherein the metal gate layer has a top side and a bottom side (TS21 and BS21 in annotated Fig. 1); wherein the interlayer has a top side and a bottom side (TS22 and BS22 in annotated Fig. 1); wherein the p-type doped Gallium Nitride layer has a top side and a bottom side (TS24 and BS24 in annotated Fig. 1); wherein the bottom side of the metal gate layer is disposed on the top side of the interlayer (Annotated Fig. 1); and wherein the bottom side of the interlayer is disposed on the top side of the p-type doped Gallium Nitride layer (Annotated Fig. 1).
Regarding Claim 15 – Tanimoto discloses the Gallium Nitride power transistor according to claim 1, wherein the metal gate layer has a top side and a bottom side; wherein the interlayer has a top side and a bottom side; and wherein the metal gate layer covers at least part of the top side of the interlayer.
Regarding Claim 18 – Tanimoto discloses the Gallium Nitride power transistor according to claim 1, wherein the buffer layer comprises a Gallium Nitride layer or an Aluminum Gallium Nitride layer ([0054]).
Regarding Claim 19 – Tanimoto discloses the Gallium Nitride power transistor according to claim 1, wherein the barrier layer comprises an Aluminum Gallium Nitride layer ([0054]).
Regarding Claim 20 – Tanimoto discloses a metal-semiconductor junction for a Gallium Nitride power transistor, the metal-semiconductor junction comprising: an interlayer (fourth nitride semiconductor layer 22 [0058] and Fig. 1) interposed between a p-type doped Gallium Nitride layer (third nitride semiconductor layer 24 [0058] and Fig. 1) and a metal gate layer (gate electrode 21 [0058] and Fig. 1), wherein the interlayer is made of a III-V compound semiconductor comprising a combination of at least one group III element with at least one group V element (e.g. AlGaN [0058]); and wherein the metal gate layer is configured to electrically connect the p-type doped Gallium Nitride layer via the interlayer to form a rectifying metal-semiconductor junction with the p-type doped Gallium Nitride layer ([0061]).
Regarding Claim 21 – Tanimoto further discloses the metal-semiconductor junction according to claim 20, wherein the at least one group III element comprises one of the following chemical elements: Aluminum, Gallium, or Indium (e.g. aluminum and gallium [0058]).
Regarding Claim 22 – Tanimoto further discloses the metal-semiconductor junction according to claim 20, wherein the at least one group V element comprises one of the following chemical elements: Nitrogen, Phosphorus, Arsenic, or Antimony (e.g. nitrogen [0058]).
Regarding Claim 23 – Tanimoto further discloses the metal-semiconductor junction according to claim 20, wherein the metal gate layer is configured to electrically connect the p-type doped Gallium Nitride layer via the interlayer to form a Schottky barrier with the p-type doped Gallium Nitride layer (Electrical connection described in [0061-0062]).
Regarding Claim 24 – Tanimoto further discloses the metal-semiconductor junction according to claim 20, wherein the rectifying metal-semiconductor junction comprises a reverse biased Schottky diode for separating the p-type doped Gallium Nitride layer from the metal gate layer (Schottky depletion layer generated [0061]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tanimoto (US 20140175455 A1, hereinafter “Tanimoto”), in view of Sayadi (US 20220199815 A1, hereinafter “Sayadi”), and further in view of MPEP 2144.06(II).
Regarding Claim 8 – Tanimoto discloses all the limitations of claim 1.
Tanimoto fails to disclose the interlayer comprises Indium-Aluminum-Nitride.
However, Sayadi discloses the group III-nitride in the Schottky gate structure (14, Sayadi [0045] and Fig. 1) may include indium along with aluminum and nitrogen (Sayadi [0044]).
Sayadi discloses an analogous compound semiconductor transistor to Tanimoto. Sayadi teaches the group III element(s) forming the nitride semiconductor layers may be selected from aluminum, gallium, indium, and boron, either alone or in combination (Sayadi [0044]). This shows that substituting indium-aluminum-nitride for aluminum-gallium-nitride as the interlayer presents a prima facie case of obviousness, as these are known equivalents in the art. See MPEP 2144.06(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider substituting indium-aluminum-nitride for aluminum-gallium-nitride as the interlayer material, since these are known equivalents in the art.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 7:30a-5p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898