Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on JP2022-147548 filed on 09/16/2022.
Election/ Restrictions
Applicant's election of group II without traverse: claims 1-14, 16-19, in the “Response to Election / Restriction Filed - 12/19/2025”, withdrawal of non-elected claim(s) 15 is/are acknowledged. This office action considers claims 1-19, in “Claims - 09/01/2023”, pending for prosecution, of which claim(s) 15 is/are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(2):
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-4, 12-13, 16, 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai et al. (US 20220376071 A1 – hereinafter Tsai).
Regarding Claim 1, Tsai teaches a semiconductor device (see the entire document; Fig. 1; specifically, [0017]-[0028], and as cited below), comprising:
a substrate (10 – Fig. 1 – [0017]);
a first transistor (T1) having:
a first diffusion layer region (left 42) and a second diffusion layer region (right 42) disposed on the substrate,
a first gate insulating film (70, part of GS1 – [0028]) disposed on the substrate and at least partially facing a region between the first diffusion layer region (left 42) and the second diffusion layer region (right 42),
a first gate electrode (MG1) located on a side opposite to the substrate with respect to the first gate insulating film (bottom part of 70), and
a first silicide layer (52 – [0023]) disposed on the first diffusion layer region (left 42)) and the second diffusion layer region (right 42); and
a second transistor (T2) having:
a third diffusion layer region (left 44) and a fourth diffusion layer region (right 44) disposed on the substrate,
a second gate insulating film (70, part of GS2 – [0028]) disposed on the substrate and at least partially facing a region between the third diffusion layer region (left 44) and the fourth diffusion layer region (right 44),
a second gate electrode (MG2) located on a side opposite to the substrate with respect to the second gate insulating film (bottom part of 70), and
a second silicide layer (54 – [0025]) disposed on the third diffusion layer region (left 44) and the fourth diffusion layer region (right 44),
wherein the first silicide layer (52) is disposed apart from the first gate insulating film (70, part of MG1), and
a distance between the first silicide layer and the first gate insulating film (DS1) is larger than a distance between the second silicide layer and the second gate insulating film (DS2 – that is, DS1>DS2 - see [0026]).
Regarding Claim 2, Tsai teaches the semiconductor device according to claim 1, wherein the first transistor and the second transistor have a same size (Applicant defines “transistors of the same size" means that a difference in thickness of gate insulating films (for example, gate insulating films 33 and 43) described below in the Z direction is 10% or less” in para. [0018] of the Specification. Tsai teaches both the gate dielectric have the same thickness as they are 70).
Regarding Claim 3, Tsai teaches the semiconductor device according to claim 1, wherein a distance between the first silicide layer and the first gate electrode in a direction from the first diffusion layer region toward the second diffusion layer region is larger than a distance between the second silicide layer and the second gate electrode in a direction from the third diffusion layer region toward the fourth diffusion layer region (since DS1>DS2).
Regarding Claim 4, Tsai teaches the semiconductor device according to claim 1, wherein the first transistor has a first insulating film (S11 – Fig. 1 – [0029]) disposed between the first silicide layer (left 52) and the first gate insulating film (MG1) on the first diffusion layer region (left 42) and the second diffusion layer region (right 42) and the first insulating film is continuous with the first gate insulating film (at least the left side of 70), and the first gate insulating film and the first insulating film are oxide films ([0028]-[0029].
Regarding Claim 12, Tsai teaches the semiconductor device according to claim 1, wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor (see – [0020]).
Regarding Claim 13, Tsai teaches the semiconductor device according to claim 12, wherein the first transistor is an n-type transistor, and the second transistor is a p-type transistor (see – [0020]).
Regarding Claim 16, Tsai teaches the semiconductor device according to claim 1, wherein the substrate includes silicon ([0027]).
Regarding Claim 19, Tsai teaches the semiconductor device according to claim 1, wherein the second gate insulating film includes silicon oxide ([0028]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 11 rejected under 35 U.S.C. 103 as being unpatentable over Tsai.
Regarding claim 11, Tsai teaches claim 1 from which claim 11 depends.
As per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Tsai discloses all the features of claim 1, therefore, the device in claim 1 will function the same way as Tsai, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Li et al. (US 20250308598 A1 - hereinafter Li).
Regarding claims 17-18, Tsai teaches claim 1 from which claim 17 depends. But Tsai does not expressly disclose wherein the semiconductor device includes a NAND flash memory and wherein the semiconductor device includes an array chip.
However, it is well known in the art to have semiconductor devices including transistors to be part of NAND flash memory array is also taught by Li (Li – see claim 10).
Allowable Subject Matter
Claims 5-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 5: The semiconductor device according to claim 4, wherein at least a part of the first insulating film is located on an inner side of the substrate in a thickness direction of the substrate as compared with the first gate insulating film.
Regarding claim 6: The semiconductor device according to claim 4, wherein a component of the first insulating film is different from a component of the first gate insulating film, and the first insulating film contains an impurity having a same polarity as an impurity in the first diffusion layer region.
Regarding claim 7: The semiconductor device according to claim 4, wherein when a thickness direction of the substrate is a first direction, a thickness of the first insulating film in the first direction is smaller than a thickness of the first gate insulating film in the first direction.
Regarding claim 8: The semiconductor device according to claim 7, wherein the thickness of the first insulating film in the first direction is smaller than a thickness of the second gate insulating film in the first direction.
Regarding claim 9: The semiconductor device according to claim 7, wherein in a case where a direction from the first diffusion layer region toward the second diffusion layer region is a second direction, a length of the first insulating film in the second direction is larger than the thickness of the first insulating film in the first direction.
Regarding claim 10: The semiconductor device according to claim 4, further comprising: a first contact electrode extending in a thickness direction of the substrate and being in contact with the first silicide layer, wherein the first insulating film has a first end in contact with the first silicide layer, and a distance between the first end and the first gate insulating film is larger than a distance between the first end and the first contact electrode.
REASON FOR ALLOWANCE
Claim 14 is allowed over prior art.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 14, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20220376071 A1 – hereinafter Tsai) substantially teach(es) some of limitations in claim 14 similar to claim 1, but not the limitations of “wherein the transistor has a first insulating film disposed between the silicide layer and the gate insulating film on the first diffusion layer region and the second diffusion layer region and is continuous with the gate insulating film, a component of the first insulating film is different from a component of the gate insulating film, and the first insulating film contains an impurity having a same polarity as an impurity in the first diffusion layer region” as recited in claim 1. Therefore, the claim 1 is deemed patentable over the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898