DETAILED ACTION
This action is responsive to the following communication: the response filed 6/10/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-14 and 17 pending, 15-16 cancelled.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/10/26 has been entered.
Election/Restrictions
Newly submitted claim 17 is directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: the claims to the different species recite the mutually exclusive characteristics of such species.
I. Claims 1-14, drawn to a first embodiment in fig. 5/6A/6B/6C, directed to a common source line.
II. Claims 17, drawn to a second embodiment in fig. 10A/10B/10C, directed to separate source lines.
Therefore, claim 17, if originally presented, would further be restricted from the originally presented claims 1-14.
There is a serious search and/or examination burden for the patentably distinct species as set forth above because at least the following reason(s) apply:
--the species or groupings of patentably indistinct species have acquired a separate status in the art in view of their different classification;
--the species or groupings of patentably indistinct species have acquired a separate status in the art due to their recognized divergent subject matter;
--the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries); and/or
--the prior art applicable to one invention would not likely be applicable to another invention.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 17 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2016/0071596) in view of Chai (US 2022/0051728).
Regarding claim 1, Lee discloses a semiconductor memory device (fig. 3, 4) comprising:
a first bit line (BL1) connected to one end (DST end) of a first string (CS11) including a first select transistor (any select transistor DST/SST), a plurality of memory cell transistors (MC1-MCn), and a second select transistor (another select transistor DST/SST);
a second bit line (BLm) connected to one end (DST end) of a second string (CS1m) including a third select transistor (any select transistor DST/SST), a plurality of memory cell transistors (MC1-MCn), and a fourth select transistor (another select transistor DST/SST);
a source line (CSL) commonly connected to the other end (SST end) of the first string (CS11) and the other end (SST end) of the second string (CS1m);
a select gate line (DSL/SSL) commonly connected to the first select transistor and the second select transistor (a common select gate line DSL commonly connects any and another select transistors DST1-DST3, a common select gate line SSL commonly connects any and another select transistors SST1-SST3);
a word line commonly (WL1-WLn) connected to respective gates of the memory cell transistors (MC1-MCn) in one or more same rows of the first string (CS11) and the second string (CS1m);
a voltage generation circuit (122; fig. 1); a row decoder (121).
Lee does not expressly disclose configured to apply a first voltage to the first bit line according to a first target level during a verification operation, apply a second voltage to the second bit line according to a second target level, and apply a third voltage to the source line simultaneously, wherein the first voltage applied during the verification operation is different from the second voltage; and configured to apply a fourth voltage to the word line to which a first one of the memory cell transistors of the first string and a second one of the memory cell transistors of the second string to be verified are connected during the verification operation.
Chai discloses (fig. 5, as modified by fig. 7) configured to apply a first voltage (VPBSENSE-VTH; fig. 7) to the first bit line (selected BL; fig. 7) according to a first target level (a target level of the first bit line) during a verification operation (VERIFY PHASE; fig. 7), apply a second voltage (VCORE; fig. 7) to the second bit line (unselected BL; fig. 7) according to a second target level (a target level of the second bit line), and apply a third voltage (VDSL; fig. 5) to the source line (DSL, SSL; fig. 5) simultaneously (VDSL, VPBSENSE-VTH, and VCORE are considered simultaneously applied during the VERIFY PHASE, i.e. fig. 5 diagrams the first through third voltages during the VERIFY PHASE while fig.7 diagrams a modification to the second and third voltages during the VERIFY PHASE), wherein the first voltage applied during the verification operation is different from the second voltage (fig. 7); and configured to apply a fourth voltage (VVFY; fig. 5, 7) to the word line (selected WL; fig. 7) to which a first one of the memory cell transistors of the first string (BL1; fig. 3) and a second one of the memory cell transistors of the second string (BLn; fig. 3) to be verified are connected during the verification operation (during the VERIFY PHASE; fig. 5, 7).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is modifiable as taught by Chai for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0143, 0157 of Chai), which is common and well known in the prior art to achieve and efficient and robust operating device.
Regarding claim 5, Lee discloses a method for verifying (fig. 3, 4),
comprising:
connecting a first bit line (BL1) to one end (DST end) of a first string (CS11) including a first select transistor (any select transistor DST/SST), a plurality of memory cell transistors (MC1-MCn), and a second select transistor (another select transistor DST/SST);
connecting a second bit line (BLm) to one end (DST end) of a second string (CS1m) including a third select transistor(any select transistor DST/SST), a plurality of memory cell transistors (MC1-MCn), and a fourth select transistor (another select transistor DST/SST);
connecting a source line (CSL) to the other end (SST end) of the first string (CS11) and the other end (SST end) of the second string (CS1m);
connecting a select gate line (DSL/SSL) commonly to the first select transistor and the second select transistor (a common select gate line DSL commonly connects any and another select transistors DST1-DST3, a common select gate line SSL commonly connects any and another select transistors SST1-SST3);
connecting a word line (WL1-WLn) to respective gates of the memory cell transistors (MC1-MCn) in one or more same rows of the first string (CS11) and the second string (CS1m).
Lee does not expressly disclose verifying memory cell transistors; applying a first voltage to the first bit line according to a first target level during a verification operation, applying a second voltage to the second bit line according to a second target level, and applying a third voltage to the source line simultaneously, wherein the first voltage applied during the verification operation is different from the second voltage; and applying a fourth voltage to the word line to which a first one and a second one of the memory cell transistors to be verified are connected during the verification operation.
Chai discloses verifying memory cell transistors (fig. 5, as modified by fig. 7); applying a first voltage (VPBSENSE-VTH; fig. 7) to the first bit line (selected BL; fig. 7) according to a first target level (a target level of the first bit line) during a verification operation (VERIFY PHASE; fig. 7), applying a second voltage (VCORE; fig. 7) to the second bit line (unselected BL; fig. 7) according to a second target level (a target level of the second bit line), and applying a third voltage (VDSL; fig. 5) to the source line (DSL, SSL; fig. 5) simultaneously (VDSL, VPBSENSE-VTH, and VCORE are considered simultaneously applied during the VERIFY PHASE, i.e. fig. 5 diagrams the first through third voltages during the VERIFY PHASE while fig.7 diagrams a modification to the second and third voltages during the VERIFY PHASE), wherein the first voltage applied during the verification operation is different from the second voltage (fig. 7); and applying a fourth voltage (VVFY; fig. 5, 7) to the word line (selected WL; fig. 7) to which a first one of the memory cell transistors of the first string (BL1; fig. 3) and a second one of the memory cell transistors of the second string (BLn; fig. 3) to be verified are connected during the verification operation (during the VERIFY PHASE; fig. 5, 7).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is modifiable as taught by Chai for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0143, 0157 of Chai), which is common and well known in the prior art to achieve and efficient and robust operating device.
Claim(s) 10-11, 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2016/0071596), in view of Chai (US 2022/0051728), and further in view of Yoshida et al. (US 2020/0013468 ‒hereinafter Yoshida).
Regarding claim 10, Lee, as modified, does not expressly disclose the semiconductor memory device, wherein after applying the first voltage and the second voltage, the second select transistor and the fourth select transistor are turned on.
Yoshida discloses wherein after applying the first voltage and the second voltage (i.e. after VBL is applied), the second select transistor and the fourth select transistor are turned on (i.e. sense amplifier 28 applies VBL to all bit lines, ST2 is turned on, essentially including ST2 of BL0 and ST2 of BL1; para 0117).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Regarding claim 11, Lee, as modified, does not expressly disclose the semiconductor memory device, wherein after applying the first voltage and the second voltage, the third voltage is applied.
Yoshida discloses the semiconductor memory device, wherein after applying the first voltage and the second voltage (i.e. after VBL is applied), the third voltage is applied (i.e. sense amplifier 28 applies VBL to all bit lines, third voltage VSRC lower than VBL is applied; para 0017).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Regarding claim 13, Lee, as modified, does not expressly disclose the method, further comprising: after applying the first voltage and the second voltage, turning on the second select transistor and the fourth select transistor.
Yoshida discloses after applying the first voltage and the second voltage (i.e. after VBL is applied), turning on the second select transistor and the fourth select transistor (i.e. sense amplifier 28 applies VBL to all bit lines, ST2 is turned on, essentially including ST2 of BL0 and ST2 of BL1; para 0117).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Regarding claim 14, Lee, as modified, does not expressly disclose the method, further comprising: after applying the first voltage and the second voltage, applying the third voltage.
Yoshida discloses after applying the first voltage and the second voltage (i.e. after VBL is applied), applying the third voltage (i.e. sense amplifier 28 applies VBL to all bit lines, third voltage VSRC lower than VBL is applied; para 0017).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Claim(s) 2-3, 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2016/0071596), in view of Chai (US 2022/0051728), in view of Yoshida et al. (US 2020/0013468 ‒hereinafter Yoshida), and further in view of Choi (US 2022/0230691).
Regarding claim 2, Lee, as modified, does not expressly disclose the semiconductor memory device, further comprising: a first sense amplifier connected to the first bit line and including a first sense node; a second sense amplifier connected to the second bit line and including a second sense node; and a control circuit configured to determine whether verification of the first memory cell transistor of the first string is passed based on whether the first sense node is charged and determine whether verification of the second memory cell transistor of the second string is passed based on whether the second sense node is charged.
Yoshida discloses a first sense amplifier (SA; fig. 6) connected to the first bit line (BL0) and including a first sense node (SEN coupled to BL, i.e. BL0; fig. 6, 7); a second sense amplifier (SA; fig. 6) connected to the second bit line (BL1) and including a second sense node (SEN coupled to BL, i.e. BL1; fig. 6, 7); and a control circuit (22; fig. 2) configured to determine whether verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS; fig. 3) is passed (verify pass; para 0096) and determine whether verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS; fig. 3) is passed (verify pass; para 0096).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Choi discloses based on whether the first sense node (sense node SO coupled to a bit line, i.e. a first bit line BL1; fig. 5, 6) is charged (verification is passed based on whether sense node SO remains charged at precharge level or discharged; para 0144) and based on whether the second sense node (another sense node SO coupled to another bit line, i.e. a second bit line BL2; fig. 5, 6) is charged (verification is passed based on whether another sense node SO remains charged at precharge level or discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 3, Yoshida discloses the semiconductor memory device, wherein the control circuit is configured to determine that verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS; fig. 3) is failed (verify failed; para 0096), and determine that verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS) is passed (verify pass; para 0096).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Choi discloses is failed when the first sense node is charged (i.e. FAIL-MC when sense node SO charged at precharge level; para 0144), is passed when the first sense node is not charged (i.e. PASS-MC when sense node SO discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 4, Yoshida discloses the semiconductor memory device, wherein the control circuit is configured to determine that verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS; fig. 3) is failed (verify failed; para 0096), and determine that verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS) is passed (verify pass; para 0096).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Choi discloses is failed when the second sense node is charged (i.e. FAIL-MC when sense node SO charged at precharge level; para 0144), is passed when the second sense node is not charged (i.e. PASS-MC when sense node SO discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 6, Lee, as modified, does not expressly disclose the method, further comprising: determining whether verification of the first memory cell transistor of the first string is passed based on whether a first sense node of a first sense amplifier connected to the first bit line is charged; and determining whether verification of the second memory cell transistor of the second string is passed based on whether a second sense node of a second sense amplifier connected to the second bit line is charged.
Yoshida discloses determining whether verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS; fig. 3) is passed (verify pass; para 0096) based on whether a first sense node (SEN coupled to BL, i.e. BL0; fig. 6, 7) of a first sense amplifier (SA; fig. 6) connected to the first bit line (BL0); and determining whether verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS; fig. 3) is passed (verify pass; para 0096) based on whether a second sense node (SEN coupled to BL, i.e. BL1; fig. 6, 7) of a second sense amplifier (SA; fig. 6) connected to the second bit line (BL1).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Choi discloses based on whether the first sense node (sense node SO coupled to a bit line, i.e. a first bit line BL1; fig. 5, 6) is charged (verification is passed based on whether sense node SO remains charged at precharge level or discharged; para 0144) and based on whether the second sense node (another sense node SO coupled to another bit line, i.e. a second bit line BL2; fig. 5, 6) is charged (verification is passed based on whether another sense node SO remains charged at precharge level or discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 7, Yoshida discloses the method, further comprising: determining that verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS; fig. 3) is failed (verify failed; para 0096), and determining that verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS) is passed (verify pass; para 0096).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Choi discloses is failed when the first sense node is charged (i.e. FAIL-MC when sense node SO charged at precharge level; para 0144), is passed when the first sense node is not charged (i.e. PASS-MC when sense node SO discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 8, Yoshida discloses the method, further comprising: determining that verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS; fig. 3) is failed (verify failed; para 0096), and determining that verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS) is passed (verify pass; para 0096).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Yoshida for the purpose of facilitating data accessing schemes by reducing a time consumed in a program operation (para 0124 of Yoshida), which is common and well known in the prior art to achieve and efficient and robust operating device.
Choi discloses is failed when the second sense node is charged (i.e. FAIL-MC when sense node SO charged at precharge level; para 0144), is passed when the second sense node is not charged (i.e. PASS-MC when sense node SO discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Claim(s) 9, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2016/0071596) in view of Chai (US 2022/0051728), and further in view of Achter et al. (US 2014/0254288 ‒hereinafter Achter).
Regarding claim 9, Lee, as modified, does not expressly disclose the semiconductor memory device, further comprising: a first transistor provided between the voltage generation circuit and the first bit line, and a second transistor provided between the voltage generation circuit and the second bit line, wherein after applying the first voltage and the second voltage, the first transistor and the second transistor are turned off.
Achter discloses a first transistor (bit line driver 431, detailed as bit line driver 500, comprises transistors 501-504, i.e. essentially a first transistor; fig. 5) provided between the voltage generation circuit (421-423/410; fig. 4, 5) and the first bit line (B1; fig. 4), and a second transistor (bit line driver 432, detailed as bit line driver 500, comprises transistors 501-504, i.e. essentially a second transistor; fig. 5) provided between the voltage generation circuit (421-423/410) and the second bit line (B2; fig. 4), wherein after applying the first voltage and the second voltage, the first transistor and the second transistor are turned off (after applying any of voltages V1-V3, transistors 521-503 are de-asserted, i.e. turned off; para 0031).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Achter for the purpose of facilitating data accessing schemes by dynamically providing stable operating voltages to optimize current memory operating conditions, which in turn increases performance speeds (para 0027 of Achter).
Regarding claim 12, Lee, as modified, does not expressly disclose the method, further comprising: after applying the first voltage and the second voltage, turning off a first transistor and a second transistor, wherein the first transistor is provided between a voltage generation circuit and the first bit line, and the second transistor is provided between the voltage generation circuit and the second bit line.
Achter discloses after applying the first voltage and the second voltage, turning off a first transistor and a second transistor (after applying any of voltages V1-V3, transistors 521-503 are de-asserted, i.e. turned off; para 0031, further bit line driver 431, detailed as bit line driver 500, comprises transistors 501-504, i.e. essentially a first transistor and bit line driver 432, detailed as bit line driver 500, comprises transistors 501-504, i.e. essentially a second transistor; fig. 5), wherein the first transistor (i.e. of driver 431) is provided between a voltage generation circuit (421-423/410; fig. 4, 5) and the first bit line (B1; fig. 4), and the second transistor (i.e. of driver 432) is provided between the voltage generation circuit (421-423/410) and the second bit line (B2; fig. 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Achter for the purpose of facilitating data accessing schemes by dynamically providing stable operating voltages to optimize current memory operating conditions, which in turn increases performance speeds (para 0027 of Achter).
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824
Prosecution Insights