DETAILED ACTION
This action is responsive to the following communication: the response filed 10/14/25. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-14 pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 10-11, 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 2020/0013468 ‒hereinafter Yoshida) in view of Chai (US 2022/0051728).
Regarding claim 1, Yoshida discloses a semiconductor memory device comprising:
a first bit line (BL0; fig. 3) connected to one end of a first string (NS; fig. 3) including a first select transistor (ST1; fig. 3), a plurality of memory cell transistors (MT0-MT7; fig. 3), and a second select transistor (ST2; fig. 3);
a second bit line (BL1; fig. 3) connected to one end of a second string (another NS, coupled to BL1; fig. 3) including a third select transistor (ST1, coupled to BL1; fig. 3), a plurality of memory cell transistors (MT0-MT7, coupled to BL1; fig. 3), and a fourth select transistor (ST2, coupled to BL1; fig. 3);
a source line (SL; fig. 3) commonly connected to the other end of the first string (BL0) and the other end of the second string (BL1);
a word line (any of a word line WL0-WL7; fig. 3) commonly connected to respective gates of the memory cell transistors (MT0-MT7) in one or more same rows (i.e. as any of a respective cell unit CU; fig. 3) of the first string (NS) and the second string (second NS);
a voltage generation circuit (25; fig. 2) configured to apply a first voltage (VBL; fig. 11) to the first bit line (BL0, i.e. BL(Prog_A); fig. 11) according to a first target level (target level of state “A”; fig. 10, 11, para 0117) during a verification operation (VERIFY operation from time t5-t7; fig. 11), apply a second voltage (VBL; fig. 11) to the second bit line (BL1, i.e. BL(Prog_B); fig. 11) according to a second target level (target level of state “B”; fig. 10, 11, para 0117), and apply a third voltage (VSRC; para 0117) to the source line (SL); and
a row decoder (26; fig. 2) configured to apply a fourth voltage (VA/VB; fig. 11) to the word line (i.e. WL_sel; fig. 11) to which a first one (any first memory cell transistor connected to WL_sel) of the memory cell transistors (MT0-MT7) of the first string (BL0) and a second one (any second memory cell transistor connected to WL_sel) of the memory cell transistors (MT0-MT7) of the second string (BL1) to be verified are connected during the verification operation (para 0117).
Yoshida does not expressly disclose wherein the first voltage applied during the verification operation is different from the second voltage.
Chai discloses wherein the first voltage (VPBSENSE-VTH applied to selected BL; fig. 7) applied during (i.e. throughout a duration) the verification operation (VERIFY PHASE; fig. 7) is different from the second voltage (VCORE applied to unselected BLs; fig. 7).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is modifiable as taught by Chai for the purpose of facilitating data accessing schemes by reducing operation times (para 0157 of Chai), which benefits the commonly understood advantage of having an efficient and robust operating device.
Regarding claim 5, Yoshida discloses a method for verifying memory cell transistors, comprising:
connecting a first bit line (BL0; fig. 3) to one end of a first string (NS; fig. 3) including a first select transistor (ST1; fig. 3), a plurality of memory cell transistors (MT0-MT7; fig. 3), and a second select transistor (ST2; fig. 3);
connecting a second bit line (BL1; fig. 3) to one end of a second string (another NS, coupled to BL1; fig. 3) including a third select transistor (ST1, coupled to BL1; fig. 3), a plurality of memory cell transistors (MT0-MT7, coupled to BL1; fig. 3), and a fourth select transistor (ST2, coupled to BL1; fig. 3);
connecting a source line (SL; fig. 3) to the other end of the first string (BL0) and the other end of the second string (BL1);
connecting a word line (any of a word line WL0-WL7; fig. 3) to respective gates of the memory cell transistors (MT0-MT7) in one or more same rows (i.e. as any of a respective cell unit CU; fig. 3) of the first string (NS) and the second string (second NS);
applying a first voltage (VBL; fig. 11) to the first bit line (BL0, i.e. BL(Prog_A); fig. 11) according to a first target level (target level of state “A”; fig. 10, 11, para 0117) during a verification operation (VERIFY operation from time t5-t7; fig. 11), applying a second voltage (VBL; fig. 11) to the second bit line (BL1, i.e. BL(Prog_B); fig. 11) according to a second target level (target level of state “B”; fig. 10, 11, para 0117), and applying a third voltage (VSRC; para 0117) to the source line (SL); and
applying a fourth voltage (VA/VB; fig. 11) to the word line (i.e. WL_sel; fig. 11) to which a first one (any first memory cell transistor connected to WL_sel) and a second one (any second memory cell transistor connected to WL_sel) of the memory cell transistors (MT0-MT7) to be verified are connected during the verification operation (para 0117).
Yoshida does not expressly disclose wherein the first voltage applied during the verification operation is different from the second voltage.
Chai discloses wherein the first voltage (VPBSENSE-VTH applied to selected BL; fig. 7) applied during (i.e. throughout a duration) the verification operation (VERIFY PHASE; fig. 7) is different from the second voltage (VCORE applied to unselected BLs; fig. 7).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is modifiable as taught by Chai for the purpose of facilitating data accessing schemes by reducing operation times (para 0157 of Chai), which benefits the commonly understood advantage of having an efficient and robust operating device.
Regarding claim 10, Yoshida discloses the semiconductor memory device, wherein after applying the first voltage and the second voltage (i.e. after VBL is applied), the second select transistor and the fourth select transistor are turned on (i.e. sense amplifier 28 applies VBL to all bit lines, ST2 is turned on, essentially including ST2 of BL0 and ST2 of BL1; para 0117).
Regarding claim 11, Yoshida discloses the semiconductor memory device, wherein after applying the first voltage and the second voltage (i.e. after VBL is applied), the third voltage is applied (i.e. sense amplifier 28 applies VBL to all bit lines, third voltage VSRC lower than VBL is applied; para 0017).
Regarding claim 13, Yoshida discloses the method, further comprising: after applying the first voltage and the second voltage (i.e. after VBL is applied), turning on the second select transistor and the fourth select transistor (i.e. sense amplifier 28 applies VBL to all bit lines, ST2 is turned on, essentially including ST2 of BL0 and ST2 of BL1; para 0117).
Regarding claim 14, Yoshida discloses the method, further comprising: after applying the first voltage and the second voltage (i.e. after VBL is applied), applying the third voltage (i.e. sense amplifier 28 applies VBL to all bit lines, third voltage VSRC lower than VBL is applied; para 0017).
Claim(s) 2-3, 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 2020/0013468 ‒hereinafter Yoshida) in view of Chai (US 2022/0051728), and further in view of Choi (US 2022/0230691).
Regarding claim 2, Yoshida discloses the semiconductor memory device, further comprising: a first sense amplifier (SA; fig. 6) connected to the first bit line (BL0) and including a first sense node (SEN coupled to BL, i.e. BL0; fig. 6, 7); a second sense amplifier (SA; fig. 6) connected to the second bit line (BL1) and including a second sense node (SEN coupled to BL, i.e. BL1; fig. 6, 7); and a control circuit (22; fig. 2) configured to determine whether verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS; fig. 3) is passed (verify pass; para 0096) and determine whether verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS; fig. 3) is passed (verify pass; para 0096).
Yoshida, as modified, does not expressly disclose based on whether the first sense node is charged and based on whether the second sense node is charged.
Choi discloses based on whether the first sense node (sense node SO coupled to a bit line, i.e. a first bit line BL1; fig. 5, 6) is charged (verification is passed based on whether sense node SO remains charged at precharge level or discharged; para 0144) and based on whether the second sense node (another sense node SO coupled to another bit line, i.e. a second bit line BL2; fig. 5, 6) is charged (verification is passed based on whether another sense node SO remains charged at precharge level or discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 3, Yoshida discloses the semiconductor memory device, wherein the control circuit is configured to determine that verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS; fig. 3) is failed (verify failed; para 0096), and determine that verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS) is passed (verify pass; para 0096).
Yoshida, as modified, does not expressly disclose is failed when the first sense node is charged, is passed when the first sense node is not charged.
Choi discloses is failed when the first sense node is charged (i.e. FAIL-MC when sense node SO charged at precharge level; para 0144), is passed when the first sense node is not charged (i.e. PASS-MC when sense node SO discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 4, Yoshida discloses the semiconductor memory device, wherein the control circuit is configured to determine that verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS; fig. 3) is failed (verify failed; para 0096), and determine that verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS) is passed (verify pass; para 0096).
Yoshida, as modified, does not expressly disclose is failed when the second sense node is charged, is passed when the second sense node is not charged.
Choi discloses is failed when the second sense node is charged (i.e. FAIL-MC when sense node SO charged at precharge level; para 0144), is passed when the second sense node is not charged (i.e. PASS-MC when sense node SO discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 6, Yoshida discloses the method, further comprising: determining whether verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS; fig. 3) is passed (verify pass; para 0096) based on whether a first sense node (SEN coupled to BL, i.e. BL0; fig. 6, 7) of a first sense amplifier (SA; fig. 6) connected to the first bit line (BL0); and determining whether verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS; fig. 3) is passed (verify pass; para 0096) based on whether a second sense node (SEN coupled to BL, i.e. BL1; fig. 6, 7) of a second sense amplifier (SA; fig. 6) connected to the second bit line (BL1).
Yoshida, as modified, does not expressly disclose based on whether the first sense node is charged and based on whether the second sense node is charged.
Choi discloses based on whether the first sense node (sense node SO coupled to a bit line, i.e. a first bit line BL1; fig. 5, 6) is charged (verification is passed based on whether sense node SO remains charged at precharge level or discharged; para 0144) and based on whether the second sense node (another sense node SO coupled to another bit line, i.e. a second bit line BL2; fig. 5, 6) is charged (verification is passed based on whether another sense node SO remains charged at precharge level or discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 7, Yoshida discloses the method, further comprising: determining that verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS; fig. 3) is failed (verify failed; para 0096), and determining that verification of the first memory cell transistor (any first memory cell transistor connected to WL_sel) of the first string (NS) is passed (verify pass; para 0096).
Yoshida, as modified, does not expressly disclose is failed when the first sense node is charged, is passed when the first sense node is not charged.
Choi discloses is failed when the first sense node is charged (i.e. FAIL-MC when sense node SO charged at precharge level; para 0144), is passed when the first sense node is not charged (i.e. PASS-MC when sense node SO discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Regarding claim 8, Yoshida discloses the method, further comprising: determining that verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS; fig. 3) is failed (verify failed; para 0096), and determining that verification of the second memory cell transistor (any second memory cell transistor connected to WL_sel) of the second string (another NS) is passed (verify pass; para 0096).
Yoshida, as modified, does not expressly disclose is failed when the second sense node is charged, is passed when the second sense node is not charged.
Choi discloses is failed when the second sense node is charged (i.e. FAIL-MC when sense node SO charged at precharge level; para 0144), is passed when the second sense node is not charged (i.e. PASS-MC when sense node SO discharged; para 0144).
Charging and discharging of sense nodes, along with pass/fail verifications are common and well known in the prior art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is further modifiable as taught by Choi for the purpose of facilitating data accessing schemes by improving performance speeds, which benefits the commonly understood advantage of reducing the overall operation time required for data access (para 0023, 0155 of Choi).
Claim(s) 9, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 2020/0013468 ‒hereinafter Yoshida) in view of Chai (US 2022/0051728), and further in view of Achter et al. (US 2014/0254288 ‒hereinafter Achter).
Regarding claim 9, Yoshida, as modified, does not expressly disclose the semiconductor memory device, further comprising: a first transistor provided between the voltage generation circuit and the first bit line, and a second transistor provided between the voltage generation circuit and the second bit line, wherein after applying the first voltage and the second voltage, the first transistor and the second transistor are turned off.
Achter discloses a first transistor (bit line driver 431, detailed as bit line driver 500, comprises transistors 501-504, i.e. essentially a first transistor; fig. 5) provided between the voltage generation circuit (421-423/410; fig. 4, 5) and the first bit line (B1; fig. 4), and a second transistor (bit line driver 432, detailed as bit line driver 500, comprises transistors 501-504, i.e. essentially a second transistor; fig. 5) provided between the voltage generation circuit (421-423/410) and the second bit line (B2; fig. 4), wherein after applying the first voltage and the second voltage, the first transistor and the second transistor are turned off (after applying any of voltages V1-V3, transistors 521-503 are de-asserted, i.e. turned off; para 0031).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is further modifiable as taught by Achter for the purpose of facilitating data accessing schemes by dynamically providing stable operating voltages to optimize current memory operating conditions, which in turn increases performance speeds (para 0027 of Achter).
Regarding claim 12, Yoshida, as modified, does not expressly disclose the method, further comprising: after applying the first voltage and the second voltage, turning off a first transistor and a second transistor, wherein the first transistor is provided between a voltage generation circuit and the first bit line, and the second transistor is provided between the voltage generation circuit and the second bit line.
Achter discloses after applying the first voltage and the second voltage, turning off a first transistor and a second transistor (after applying any of voltages V1-V3, transistors 521-503 are de-asserted, i.e. turned off; para 0031, further bit line driver 431, detailed as bit line driver 500, comprises transistors 501-504, i.e. essentially a first transistor and bit line driver 432, detailed as bit line driver 500, comprises transistors 501-504, i.e. essentially a second transistor; fig. 5), wherein the first transistor (i.e. of driver 431) is provided between a voltage generation circuit (421-423/410; fig. 4, 5) and the first bit line (B1; fig. 4), and the second transistor (i.e. of driver 432) is provided between the voltage generation circuit (421-423/410) and the second bit line (B2; fig. 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Yoshida is further modifiable as taught by Achter for the purpose of facilitating data accessing schemes by dynamically providing stable operating voltages to optimize current memory operating conditions, which in turn increases performance speeds (para 0027 of Achter).
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______