DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 09/01/2023.
Currently claims 1-20 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/19/2023 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 14-20 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 14, the instant claim recites “…zirconium O" (claim 14, line 9). It unclear what is “zirconium O”. Is it “zirconium oxide” or “O” is a typographical error, rendering the claim indefinite. Clarification and/or correction are/is required. For the purpose of examination, the claim will be interpreted as “zirconium oxide”.
Claims 15-20 are also rejected due to their dependence on a rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0328006 A1 (Hwang) and further in view of US 2011/0140068 A1 (Ozawa).
Regarding claim 1, Hwang discloses, a nonvolatile semiconductor memory (MC; memory cell; Fig. 4C; [0044] – [0047]), comprising:
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a first electrode (11; first electrode; Fig. 4C; [0045]);
a second electrode (13; second electrode; Fig. 4C; [0045]) spaced from the first electrode (11); and
a memory element (200; memory cell; Fig. 4C; [0045]) and a switching element (100; switching unit; Fig. 4C; [0045]) between the first electrode (11) and the second electrode (13),
wherein the switching element (100) includes a tunnel insulating film (12; bipolar tunneling layer; Fig. 4C; [0045]), and
the tunnel insulating film (12) includes at least one of tantalum, titanium, and zirconium ([0023]), and further includes oxygen ([0023]).
Note: Hwang teaches tunneling layer 12 includes zirconium oxide layer (ZrO2), a titanium oxide layer (TiO2), and a tantalum oxide layer (Ta2O5).
But Hwang fails to teach explicitly, the tunnel insulating film further includes yttrium,
However, in analogous art, Ozawa discloses, the tunnel insulating film (23a; tunnel insulating film; Fig. 3A; [0038]) further includes yttrium ([0038]),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hwang and Ozawa before him/her, to modify the teachings of a memory device using a switching element having a tunnel insulating film as taught by Hwang and to include the teachings of tunnel insulating film includes yttrium as taught by Ozawa since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Hwang, a person with ordinary skill in the art would be motivated to reach out to Ozawa while forming a memory device of Hwang.
Regarding claim 2, Hwang discloses, the nonvolatile semiconductor memory according to claim 1, wherein the tunnel insulating film (12) includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]).
Regarding claim 3, Hwang discloses, the nonvolatile semiconductor memory according to claim 2, wherein the first insulating film (12A and 12B) comprises a plurality of layers (Fig. 4C; [0020]).
Regarding claim 5, the combination of Hwang and Ozawa discloses, the nonvolatile semiconductor memory according to claim 1,
wherein the tunnel insulating film (12) includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]; Hwang Ref.), and
at least one of the first insulating film and the second insulating film (12A, 12B and 12C) comprises Ta, O (Hwang; [0023]), Y (Ozawa; [0038]), and at least one element selected from the group consisting of Hf, Zr, Sc, Nb, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu (Hf or Zr; Hwang; [0023]).
Regarding claim 6, the combination of Hwang and Ozawa discloses, the nonvolatile semiconductor memory according to claim 1,
wherein the tunnel insulating film (12) includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]; Hwang Ref.), and
at least one of the first insulating film and the second insulating film (12A, 12B and 12C) comprises Ti, O (Hwang; [0023]), Y (Ozawa; [0038]), and at least one element selected from the group consisting of Hf, Zr, Sc, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu (Hf or Zr; Hwang; [0023]).
Regarding claim 7, the combination of Hwang and Ozawa discloses, the nonvolatile semiconductor memory according to claim 1,
wherein the tunnel insulating film (12) includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]; Hwang Ref.), and
at least one of the first insulating film and the second insulating film (12A, 12B and 12C) comprises Zr, O (Hwang; [0023]), Y (Ozawa; [0038]), and at least one element selected from the group consisting of Hf, Sc, and La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu (Hf; Hwang; [0023]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0328006 A1 (Hwang) and further in view of US 2013/0240972 A1 (Toratani).
Regarding claim 1, Hwang discloses, a nonvolatile semiconductor memory (MC; memory cell; Fig. 4C; [0044] – [0047]), comprising:
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a first electrode (11; first electrode; Fig. 4C; [0045]);
a second electrode (13; second electrode; Fig. 4C; [0045]) spaced from the first electrode (11); and
a memory element (200; memory cell; Fig. 4C; [0045]) and a switching element (100; switching unit; Fig. 4C; [0045]) in series between the first electrode (11) and the second electrode (13),
wherein the switching element (100) includes a tunnel insulating film (12; bipolar tunneling layer; Fig. 4C; [0045]), and
the tunnel insulating film (12) includes at least one of tantalum, titanium, and zirconium ([0023]), and further includes oxygen ([0023]).
Note: Hwang teaches tunneling layer 12 includes zirconium oxide layer (ZrO2), a titanium oxide layer (TiO2), and a tantalum oxide layer (Ta2O5).
But Hwang fails to teach explicitly, the tunnel insulating film further includes tungsten,
However, in analogous art, Toratani discloses, the tunnel insulating film (50; tunnel insulating film; Fig. 1B; [0016]) further includes tungsten ([0016]),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hwang and Toratani before him/her, to modify the teachings of a memory device using a switching element having a tunnel insulating film as taught by Hwang and to include the teachings of tunnel insulating film includes tungsten as taught by Toratani since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Hwang, a person with ordinary skill in the art would be motivated to reach out to Toratani while forming a memory device of Hwang.
Regarding claim 9, Hwang discloses, the nonvolatile semiconductor memory according to claim 8, wherein the tunnel insulating film (12) includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]).
Claims 14-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0328006 A1 (Hwang) and further in view of US 2011/0140068 A1 (Ozawa) and US 2013/0240972 A1 (Toratani).
Regarding claim 14, Regarding claim 1, Hwang discloses, a nonvolatile semiconductor memory (MC; memory cell; Fig. 4C; [0044] – [0047]), comprising:
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a first electrode (11; first electrode; Fig. 4C; [0045]);
a second electrode (13; second electrode; Fig. 4C; [0045]) spaced from the first electrode (11); and
a memory element (200; memory cell; Fig. 4C; [0045]) and a switching element (100; switching unit; Fig. 4C; [0045]) between the first electrode (11) and the second electrode (13),
wherein the switching element (100) includes a tunnel insulating film (12; bipolar tunneling layer; Fig. 4C; [0045]), and
the tunnel insulating film comprises oxygen (part of TiO2 and TaO2; [0023]), and at least one of tantalum, titanium, and zirconium O ([0023]).
But Hwang fails to teach explicitly, the tunnel insulating film further includes yttrium,
However, in analogous art, Ozawa discloses, the tunnel insulating film (23a; tunnel insulating film; Fig. 3A; [0038]) further includes yttrium ([0038]),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hwang and Ozawa before him/her, to modify the teachings of a memory device using a switching element having a tunnel insulating film as taught by Hwang and to include the teachings of tunnel insulating film includes yttrium as taught by Ozawa since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Hwang, a person with ordinary skill in the art would be motivated to reach out to Ozawa while forming a memory device of Hwang.
But the combination of Hwang and Ozawa fails to teach explicitly, the tunnel insulating film further includes tungsten,
However, in analogous art, Toratani discloses, the tunnel insulating film (50; tunnel insulating film; Fig. 1B; [0016]) further includes tungsten ([0016]),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hwang, Ozawa and Toratani before him/her, to modify the teachings of a memory device using a switching element having a tunnel insulating film as taught by Hwang and to include the teachings of tunnel insulating film includes tungsten as taught by Toratani since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Hwang, a person with ordinary skill in the art would be motivated to reach out to Toratani while forming a memory device of Hwang.
Regarding claim 15, Hwang discloses, the nonvolatile semiconductor memory according to claim 14, wherein the tunnel insulating film (12) includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]), and the first insulating film (12A and 12B) comprises a plurality of layers (Fig. 4C; [0020]).
Regarding claim 17, the combination of Hwang, Ozawa and Toratani teaches, the nonvolatile semiconductor memory according to claim 14, wherein the tunnel insulating film includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]), and at least one of the first insulating film and the second insulating film (12A, 12B and 12C) comprises Ta, O (Hwang; [0023]), Y (Ozawa; [0038]), W ([0016]; Toratani) and at least one element selected from the group consisting of Hf, Zr, Sc, Nb, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu (Hf or Zr; Hwang; [0023]), or at least one of Mo and Cr.
Regarding claim 18, the combination of Hwang, Ozawa and Toratani teaches, the nonvolatile semiconductor memory according to claim 14, wherein the tunnel insulating film includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]), and at least one of the first insulating film and the second insulating film (12A, 12B and 12C) comprises Ti, O (Hwang; [0023]), Y (Ozawa; [0038]), W ([0016]; Toratani) or any element selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), Hf, Zr, Sc, Nb Mo, and Cr (Hf or Zr; Hwang; [0023]).
Regarding claim 19, Hwang discloses, the nonvolatile semiconductor memory according to claim 14, wherein the tunnel insulating film includes a first insulating film (12A and 12B) and a second insulating film (12C) (Fig. 4C; [0019]), and at least one of the first insulating film and the second insulating film (12A, 12B and 12C) includes Zr, O (Hwang; [0023]), and Y (Ozawa; [0038]) and an element selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Zr, Sc, Nb, W, Mo, and Cr (Hf or Zr; Hwang; [0023]).
Regarding claim 20, Hwang discloses, the nonvolatile semiconductor memory according to claim 14, wherein the memory element (200) includes a variable resistance element (15; variable resistance layer; Fig. 4C; [0048]), a magnetoresistive element, or a phase change element.
Allowable Subject Matter
Claims 4, 10-13 and 16 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 4, the closest prior art, US 2013/0328006 A1 (Hwang), in combination with US 2011/0140068 A1 (Ozawa) and US 2013/0240972 A1 (Toratani), fails to disclose, “the nonvolatile semiconductor memory according to claim 1, wherein the relationship 0.1 ≤ A_Y/(A_Y + A_Ta) ≤ 0.3 is satisfied, when A_Y is the molar composition of yttrium in the switching element and A_Ta is the molar composition of tantalum in the switching element”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 10, the closest prior art, US 2013/0328006 A1 (Hwang), in combination with US 2011/0140068 A1 (Ozawa) and US 2013/0240972 A1 (Toratani), fails to disclose, “the nonvolatile semiconductor memory according to claim 8, wherein the relationship 0.02 ≤ A_W/(A_W + A_Ta) ≤ 0.06 is satisfied, when A_W is the molar composition of tungsten in the switching element and A_Ta is the molar composition of tantalum in the switching element”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 11, the closest prior art, US 2013/0328006 A1 (Hwang), in combination with US 2011/0140068 A1 (Ozawa) and US 2013/0240972 A1 (Toratani), fails to disclose, “the nonvolatile semiconductor memory according to claim 8, wherein the tunnel insulating film includes a first insulating film and a second insulating film, and at least one of the first insulating film and the second insulating film comprises Ta, O, W, and at least one of Mo and Cr”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 12, the closest prior art, US 2013/0328006 A1 (Hwang), in combination with US 2011/0140068 A1 (Ozawa) and US 2013/0240972 A1 (Toratani), fails to disclose, “the nonvolatile semiconductor memory according to claim 8, wherein the tunnel insulating film includes a first insulating film and a second insulating film, and at least one of the first insulating film and the second insulating film comprises Ti, O, W, and at least one element selected from the group consisting of V, Nb, Mo, and Cr”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 13, the closest prior art, US 2013/0328006 A1 (Hwang), in combination with US 2011/0140068 A1 (Ozawa) and US 2013/0240972 A1 (Toratani), fails to disclose, “the nonvolatile semiconductor memory according to claim 8, wherein the tunnel insulating film includes a first insulating film and a second insulating film, and at least one of the first insulating film and the second insulating film comprises Zr, O, W, and at least one element selected from the group consisting of V, Nb, Mo, and Cr”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 16, the closest prior art, US 2013/0328006 A1 (Hwang), in combination with US 2011/0140068 A1 (Ozawa) and US 2013/0240972 A1 (Toratani), fails to disclose, “the nonvolatile semiconductor memory according to claim 14, wherein the relationships 0.1 ≤ A_Y/(A_Y + A_Ta) ≤ 0.3 and 0.02 ≤ A_W/(A_W + A_Ta) ≤ 0.06 are satisfied, where A_Y is the molar composition of yttrium in the switching element, A_W is the molar composition of tungsten in the switching element, and A_Ta is the molar composition of tantalum in the switching element”, in combination with the additionally claimed features, as are claimed by the Applicant.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2013/0237047 A1 (Nakao) - A nonvolatile semiconductor memory device is disclosed including a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.
US 2012/0139029 A1 (Yaegashi) - A nonvolatile semiconductor memory is disclosed including a memory cell including, a charge storage layer on a gate insulating film, a multilayer insulator on the charge storage layer, and a control gate electrode on the multilayer insulator, the gate insulating film including a first tunnel film, a first high-dielectric-constant film on the first tunnel film and offering a greater dielectric constant than the first tunnel film, and a second tunnel film on the first high-dielectric-constant film and having the same configuration as that of the first tunnel film, the multilayer insulator including a first insulating film, a second high-dielectric-constant film on the first insulating film and offering a greater dielectric constant than the first insulating film, and a second insulating film on the second high-dielectric-constant film and having the same configuration as that of the first insulating film.
US 2012/0025297 A1 (Takashima) - A nonvolatile semiconductor memory device is disclosed including a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
02/10/2026