Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant’s election without traverse of Group I, Embodiment 1 (figs. 7-28) which corresponds to claims 1-15 in the reply filed on 01/09/2026 is acknowledged. Therefore, claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1-15 are rejected under 35 U.S.C. 102(a1) as being anticipated by Song et al. (US 10,665,592; hereinafter Song).
Regarding claim 1, Song, in fig. 1B, discloses a semiconductor device, comprising: a substrate 100 including an active region ACT; a word line WL and a bit line BL that overlap the active region ACT; a bit line capping layer 137 that is disposed on the bit line BL, the bit line capping layer 137 having a first side and a second side opposite to the first side; a direct contact DC that electrically connects the active region ACT and the bit line BL to each other; and a buried contact BCT that is electrically connected to the active region ACT, wherein each of the first and second sides of the bit line capping layer 137 have asymmetric shapes.
Regarding claim 2, Song discloses wherein the first side of the bit line capping layer 137 has a concave shape, and the second side of the bit line capping layer has a flat shape (fig. 1B).
Regarding claim 3, Song discloses wherein the bit line capping layer 137 comprises: a first cap that overlaps the direct contact DC; and a second cap and a third cap that are disposed at opposite sides of the first cap, the first cap comprises a first side and a second side opposite to the first side, the first side of the first cap is concave, and the second side of the first cap has a flat shape (fig. 1B).
Regarding claim 4, Song discloses wherein the second cap and the third cap each include a first side and a second side opposite to the first side, respectively, the first side of the second cap faces the first side of the first cap, the first side of the second cap is concave, the second side of the second cap has a flat shape, the first side of the third cap faces the second side of the first cap, the first side of the third cap has a flat shape, and the second side of the third cap is concave (fig. 1B).
Regarding claim 5, Song discloses wherein the first cap, the second cap, and the third cap overlap the bit line BC, and the second cap and the third cap do not overlap the direct contact DC (fig. 1B).
Regarding claim 6, Song discloses wherein a direct contact trench 7 is formed in the substrate, the direct contact trench 7 comprises: a first portion where the direct contact DC is disposed; and a second portion and a third portion that are disposed at opposite sides of the first portion, and a height of a bottom surface of the second portion of the direct contact trench 7 and a height of a bottom surface of the third portion of the direct contact trench are different from each other (fig. 1B).
Regarding claim 7, Song discloses further comprising an element isolation layer 102 that is disposed in the substrate 100 and defines the active region ACT, wherein the first portion of the direct contact trench 7 is disposed on the active region ACT, and the second portion and the third portion of the direct contact trench 7 are disposed on the element isolation layer 102 (fig. 1B).
Regarding claim 8, Song discloses further comprising a first spacer (21/23/25) that covers side surfaces of the bit line BL and side surfaces of the bit line capping layer 137 and is disposed in the direct contact trench 7, wherein a height of the first spacer (21/23/25) disposed on a bottom surface of the second portion of the direct contact trench 7 and a height of the first spacer (21/23/25) disposed on a bottom surface of the third portion of the direct contact trench 7 are different from each other (fig. 1B).
Regarding claim 9, Song discloses further comprising a first insulation layer 5 disposed between the bit line BL and the element isolation layer 102, and wherein a thickness of the first insulation layer 5 varies according to position (fig. 1B).
Regarding claim 10, Song discloses wherein the first insulation layer 5 comprises: a first portion overlapping the bit line BL; and a second portion and a third portion disposed at opposite sides of the first portion, and a thickness of the second portion of the first insulation layer and a thickness of the third portion of the first insulation layer are different from each other (fig. 1B).
Regarding claim 11, Song discloses further comprising a second insulation layer 5 (col. 4, lines 12-20) that is disposed on the first insulation layer 5, wherein the second insulation layer overlaps the first portion of the first insulation layer and does not overlap the second portion and the third portion of the first insulation layer (fig. 1B).
Regarding claim 12, Song discloses further comprising a first spacer (21/23/25) that covers side surfaces of the bit line BL, side surfaces of the bit line capping layer 137, and side surfaces of the second insulation layer 5, and covers an upper surface of the first insulation layer 5 (fig. 1B).
Regarding claim 13, Song, in fig. 1B, discloses a semiconductor device, comprising: a substrate 100 including an active region ACT; a word line WL overlap the active region ACT; a bit line structure (BL/137) that includes a bit line BL and a bit line capping layer 137 overlapping both the active region ACT and the word line WL; a direct contact DC that is disposed in a direct contact trench 7 formed in the substrate 100 and electrically connects the active region ACT and the bit line BL to each other; a buried contact BC that is electrically connected to the active region ACT; and a spacer structure (21/23/25) that is disposed between the bit line structure (BL/137) and the buried contact BC and between the direct contact DC and the buried contact BC, wherein a first side of the bit line capping layer 137 has a concave shape, and wherein a second side of the bit line capping layer has a flat shape.
Regarding claim 14, Song discloses wherein the direct contact trench 7 is formed in the substrate 100, the direct contact trench 7 comprises: a first portion where the direct contact DC is disposed; and a second portion and a third portion that are disposed at opposite sides of the first portion, and a height of a bottom surface of the second portion of the direct contact trench 7 and a height of a bottom surface of the third portion of the direct contact trench 7 are different from each other (fig. 1B).
Regarding claim 15, Song discloses further comprising a first insulation layer 5 that is disposed between the bit line BL and the element isolation layer 102, wherein the first insulation layer 5 comprises: a first portion overlapping the bit line BL; and a second portion and a third portion disposed at opposite sides of the first portion, and wherein a thickness of the second portion of the first insulation layer 5 and a thickness of the third portion of the first insulation layer 5 are different from each other (fig. 1B).
Conclusion
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818