Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I: Claims in the reply filed on 12/17/2025 is acknowledged. Claims 14-37 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Allowable Subject Matter
Claim 39 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 39 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 39, the limitation "wherein the isolation insulation structure protrudes into the first support, and wherein the isolation insulation structure and the first support have substantially the same height" is considered indefinite because it contains contradictory limitations that render the scope of the invention unclear to a person of ordinary skill in the art. Specifically, the term "protrudes into" suggests a structural configuration where one element extends beyond the plane or boundary of another, implying a difference in height or a stepped interface. However, the subsequent clause stating that the structure and the first support have "substantially the same height" implies an overall aligned or coplanar top surface. Therefore, it is unclear whether the structure extends beyond (protrudes) or is flush with (same height) the first support. This inconsistency makes it impossible to determine the metes and bounds of the claimed invention, particularly regarding the vertical relationship between the isolation insulation structure and the first support.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-13 and 38-42 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20190067182 A1).
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CLAIM 1, 39: Lee discloses a semiconductor device comprising:
a first gate structure (¶[0027] & Fig. 2A & C – Alternating layers 11 are gate layers. The stack 11 on the left side of the slit 18/14 may be considered a first gate structure.);
a second gate structure (¶[0027] & Fig. 2A & C – Alternating layers 11 are gate layers. The stack 11 on the right side of the slit 18/14 may be considered a first gate structure.);
an isolation insulation structure slit/18 configured to extend in a first direction (e.g. Fig. 1A “II”) between the first gate structure 11 and the second gate structure 11, and to have a first width (Fig. 1A- Isolation portion 18) in a second direction (e.g. Fig. 1A “I”) intersecting the first direction (¶[0026]); and
a first support D_CH (A support as under stood analogous to a dummy channel structure.) located between the first gate structure 11 and the second gate structure 11, and configured to have a second width greater than the first width in the second direction (Fig. 1A & 1C- Width of support D+CH is shown to be greater than width 18, as portions of the support structure are present on either side of the slit 18.), wherein the isolation insulation structure protrudes into the first support (Fig. 1A depicts the slit protruding into the support in the II direction. Fig. 1C demonstrates the slit 18 protruding a depth direction perpendicular to both directions I & II.);
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wherein the first gate structure [The stack 11 on the left side of the slit 18/14 ] and the second gate structure [The stack 11 on the left side of the slit 18/14 ] are separated from each other by the isolation structure slit 18/14 and the first support D_CH.
CLAIM 2. Lee discloses a semiconductor device of claim 1, wherein a sidewall of the first support includes a recess, and the isolation insulation structure extends into the recess (Figs. 1A & 1C- e.g. The space in which the isolation extends into the support/dummy channel D_CH.).
CLAIM 3. Lee discloses a semiconductor device of claim 1, wherein, in a plan view, the first support has a circular shape, an elliptical shape, or a polygonal shape (Fig. 1A – D_CH).
CLAIM 4. Lee discloses a semiconductor device of claim 1, wherein, in a plan view, the first support has an elliptical shape, and includes a short axis extending along the first direction and a long axis extending along the second direction (Fig. 1A – D_CH – Note: Under broadest reasonable interpretation, this limitation does not provide any further structural distinction, as it may simply name designations. As established in previous claim 3, the shape may be circular. Under this scenario, the long axis will equal the short axis in length.).
CLAIM 5. Lee discloses a semiconductor device of claim 4, wherein a sidewall of the first support includes a recess located on the short axis (Fig. 1A – D_CH – The recess shown may be designated the short axis.).
CLAIM 6. Lee discloses a semiconductor device of claim 1, wherein the first support is located between a pair of isolation insulation structures, at least one of the pair of isolation insulation structures comprising the isolation insulation structure, and the pair of isolation insulation structures protrude into the first support (Fig. 1A – D_CH – The portion of isolation slit 18 portions extending away on either side of support D_CH is structurally analogous to a pair of isolation structures with the support between.).
CLAIM 7. Lee discloses a semiconductor device of claim 6, wherein a sidewall of the first support includes a pair of recesses, and the pair of isolation insulation structures extend into the recesses, respectively (Fig. 1A – D_CH – The claim does not exclude the recesses from connecting, thus the recess passing through D_CH may be partitioned into two designated penetrating from opposing sides of the support D_CH.).
CLAIM 10. Lee discloses a semiconductor device of claim 1, wherein the isolation insulation structure includes a convex portion and a concave portion on a sidewall thereof (Fig. 2A – Portion 18 of the Isolation slit, is formed to have concave and convex sidewalls as it isolates portions of the plugs 13).
CLAIM 11. Lee discloses a semiconductor device of claim 1, wherein the first support includes an oxide (¶27- Oxides are selected for insulation materials. Inside D_CH is disclosed to be a insulating material ¶31, thus would be understood to be an oxide.) .
CLAIM 12. Lee discloses a semiconductor device of claim 1, wherein the first support is located between a contact region of the first gate structure and a contact region of the second gate structure (Fig. 2A & 2C).
CLAIM 13. Lee discloses a semiconductor device of claim 1, further comprising: a channel structure configured to extend through a cell region of the first gate structure; and a second support configured to extend through a contact region of the first gate structure and including a dummy channel layer (Fig. 2A & 2C).
CLAIM 38. Lee discloses a semiconductor device of claim 1, wherein the isolation insulation structure and the first support have substantially the same height (Under a Broadest Reasonable Interpretation, "height" includes the vertical elevation of a top surface relative to a common reference plane; as shown in FIG. 1C, the isolation structure 18 and the dummy channel D_CH have substantially the same height because they share a common top surface, and the claim does not specify a particular plane of penetration nor require the structures to be co-extensive in vertical length.).
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CLAIM 39: Lee discloses a semiconductor device comprising:
a first gate 11 [left side] structure; a second gate 11 [right side] structure;
an isolation insulation 18 structure configured to extend in a first direction between the first gate structure and the second gate structure, and to have a first width in a second direction intersecting the first direction; and
a support D_CH located between the first gate structure and the second gate structure, and configured to have a second width greater than the first width in the second direction (Fig. 1A), wherein the isolation insulation structure protrudes into the first support Fig. 1C), and wherein the isolation insulation structure and the first support have substantially the same height (From the plan view of Fig 1A and cross sectional view of 1C, it is understood the top surfaces of the structures may be coplanar, thus the top surfaces are at the same height .
CLAIM 40: Lee discloses a semiconductor device comprising: a first gate 11 structure including a first contact region (terminology is arbitrary, not defining any particular boundaries or structure such that any portion of the gate could function as a contact region.); a second gate 11 structure including a second contact region (Figs. 1A & C); supports D_CH disposed between the first contact region and the second contact region; and isolation insulation 18 structures alternately arranged with the supports between the first gate structure and the second gate structure,
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wherein the first gate structure [The stack 11 on the left side of the slit 18/14 ] and the second gate structure [The stack 11 on the left side of the slit 18/14 ] are separated from each other by the isolation structure slit 18/14 and the first support D_CH.
CLAIM 41: Lee discloses a semiconductor device of claim 40, wherein each of the isolation insulation structures 18 extends in a first direction and has a first width in a second direction intersecting the first direction; and wherein each of the supports D_CH has a second width greater than the first width in the second direction (Fig. 1A)
CLAIM 42: Lee discloses a semiconductor device of claim 40, wherein the isolation insulation structures and the supports have substantially the same height(Under a Broadest Reasonable Interpretation, "height" includes the vertical elevation of a top surface relative to a common reference plane; as shown in FIG. 1C, the isolation structure 18 and the dummy channel D_CH have substantially the same height because they share a common top surface, and the claim does not specify a particular plane of penetration nor require the structures to be co-extensive in vertical length.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190067182 A1).
CLAIM 8. The semiconductor device of claim 7, however the written description may be silent upon wherein the first support has an elliptical shape, and the pair of recesses face each other along a short axis of the first support having the elliptical shape.
While the written description may not explicitly describe the geometry, the figures provided objectively depict elliptical channels and support/dummy channels. Specifically, an analysis of Fig. 1A, including a 90-degee rotation and overlay, highlights the elliptical shape, wherein a slit protrudes and passes through the shorter axis of the shape.
Although drawings are not necessarily to scale unless stated, the elliptical shape is at least suggested as an obvious shape by the provide figures. Under guidance of MPEP §2144.04, a mere change in shape, in the absence of unexpected results or benefits, would be an obvious design choice by a PHOSITA at the time of the invention.
The modification of the shape of the support and channels, whether circular or elliptical, is an obvious modification and/or determination for a PHOSITA. This change in shape is not understood to provide any further unexpected result of benefit beyond the known state of the art. Because the variation represents a predictable choice among known geometries, the claimed invention the selection and/or change of shape is recognized as obvious.
CLAIM 9. The semiconductor device of claim 1, however may be silent upon wherein the isolation insulation structure includes irregularities on a sidewall thereof. The scope of the term “irregularities” is not explicitly defined by the claim. The claim does not define any relative degree of these irregularities. The term is not explicitly understood from the written description. “irregularities” may be broadly interpreted as anything from a processing error or defect to general surface roughness.
Even if a prior art reference is silent upon the specific inclusion of “irregularities,” a PHOSITA would expect them. Some finite amount of “irregularities” would be expected by a PHOSITA at the time of the invention because such features are expected occurrences in manufacturing processes (e.g. surface roughness or processing errors), their presence in the claimed device is considered a predictable and at least a obvious expected result rather than a non-obvious innovation.
In view of the broad and undefined nature of the term “irregularities,” the claimed feature represents nothing more than a condition already expected in the art. Therefore, the inclusion of such irregularities on a sidewall is an obvious requirement that fails to distinguish the invention from what a PHOSITA would conventionally expect.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
5/15/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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