Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant’s arguments with respect to the newly amended claim(s), have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Page 13 of Applicant’s Remarks filed 2/12/2026, further define the intended scope of “a void” and define the terminology to specifically be understood as a “single space that is structurally and functionally” different than the porous type voids of Park. In light of the Applicant’s explicit definition as provided in the Remarks and amended claim language to emphasize “a void” and “the void” meeting explicit conditions, the prior art of Park is no longer applied to teach voids. However, this explicit definition does not distinguish the claimed invention over the newly cited prior art demonstrating a “single void” for the same purpose as provide for in the original prior art reference.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the indication of allowable subject matter within the claim(s) is the inclusion of the limitation “ wherein the covered portions of the first electrode and the voids vertically overlap with each other “, in all of the claims which is not found in the prior art references.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 20210257368 A1) in view of Hasnai et al. (US 20190043882 A1).
PNG
media_image1.png
484
528
media_image1.png
Greyscale
CLAIM 1. Jung et al. disclose a semiconductor device, comprising:
a lower structure SUB (Fig. 22a - ¶44).
PNG
media_image2.png
484
528
media_image2.png
Greyscale
a first cell isolation layer ILD1 and a second cell isolation layer ILD1 stacked in a direction perpendicular to the lower structure and each including a void (Fig. 22a - ¶42);
PNG
media_image3.png
484
528
media_image3.png
Greyscale
a horizontal layer SP disposed between the first cell isolation layer ILD1 and the second cell isolation layer ILD1 (Fig. 22a - ¶45);
PNG
media_image4.png
484
528
media_image4.png
Greyscale
a first horizontal conductive line GE[GE1/GE2] disposed between the first cell IDL1 isolation layer and the horizontal layer SP, and a second horizontal conductive line GE[GE1/GE2] disposed between the second cell isolation layer and the horizontal layer (Fig. 22a - ¶49);
PNG
media_image5.png
484
528
media_image5.png
Greyscale
a vertical conductive line BL coupled to a first side of the horizontal layer SP (Fig. 22a - ¶33); and
PNG
media_image6.png
484
528
media_image6.png
Greyscale
a data storage element DS[EL1/DL/EL2] (i.e. capacitor) including a first electrode EL1 coupled to a second side of the horizontal layer, and disposed between the first cell isolation layer and the second cell isolation layer (Fig. 22a - ¶36).
PNG
media_image7.png
484
528
media_image7.png
Greyscale
Jung et al. may be silent upon wherein "a first cell isolation layer and a second cell isolation layer stacked in a direction perpendicular to the lower structure and each including a void… wherein the void, the horizontal layer, and the first and second horizontal conductive lines vertically overlap with each other." However, at the time of the invention, interlayer dielectric (ILD) layers like those claimed were known to include voids. Voids, air gaps, and air spacers were commonly known modifications to ILD layers used to alter their dielectric constant.
At the time of the invention, air gaps or voids were notoriously well-known for the generic purpose of lowering the dielectric constant of the dielectric (such as silicon oxide, as used in Jung et al.). This was done to decrease parasitic capacitance between conductive elements (e.g., word lines and gates).
For support, see Hasnai et al., Figure 14 and paragraph 50, which states: “The described embodiments provide a number of advantages compared to conventional solutions. For example, replacing continuous dielectric layers between wordlines of a memory array with partial dielectric layers, e.g., dielectric layers having an air gap inside them or low-k material disposed inside them, may reduce the overall wordline capacitance. This may improve the memory device performance by reducing the time required to operate the memory device.”
PNG
media_image8.png
396
550
media_image8.png
Greyscale
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the ILD of Jung et al. with a void-containing ILD as disclosed in Hasnai et al. This is because applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to such a person at the time of filing the invention, as established in KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007)
CLAIM 2. Jung et al. in view of Hasnai et all disclose a semiconductor device of claim 1, wherein the first electrode includes a horizontally oriented cylindrical structure (Jung et al. Fig. 2 - As shown and extrapolated from figs. 2 and 22a of Jung et al. the capacitor structure DS is comprised of a plurality of cylindrical capacitor portions.)
PNG
media_image9.png
564
498
media_image9.png
Greyscale
(Ju.
CLAIM 3. Jung et al. in view of Park et all disclose a semiconductor device of claim 1, wherein the first electrode E1 includes an inner wall and a plurality of outer walls, and the outer walls of the first electrode include: covered portions that are partially covered by the first and second cell isolation layers (i.g. portion of E1 that contact ILD1), and protruding portions that are not covered by the first and second cell isolation layers (e.g. portions of E1 that is not contact with ILD1) (Jung et al. Fig. 22a ).
PNG
media_image10.png
484
528
media_image10.png
Greyscale
CLAIM 15. Jung et al. in view of Hasnai et al. disclose a semiconductor device, comprising:
a lower structure SUB (Fig. 22a);
a first cell isolation layer and a second cell isolation layer stacked in a direction perpendicular to the lower structure and each including a void (Fig. 22a – As modified by Hasnai et al. – See below);
a horizontal layer disposed between the first cell isolation layer and the second cell isolation layer (Fig. 22a);
a first horizontal conductive line disposed between the first cell isolation layer and the horizontal layer, and a second horizontal conductive line disposed between the second cell isolation layer and the horizontal layer (Fig. 22a);
a vertical conductive line coupled to a first side of the horizontal layer (Fig. 22a);
a data storage element including a first electrode coupled to a second side of the horizontal layer, and disposed between the first cell isolation layer and the second cell isolation layer (Fig. 22a) and
a void capping layer capping the voids of the first and second cell isolation layers (Fig. 22a – As modified by Hasnai et al. – See below – Note: the Void capping layer, is not clearly distinguishable from the dielectric material that the void is formed in. As a void is created it is effectively a “negative” space sealed/capped by the material of which it is within.).
Jung et al. may be silent upon wherein "a first cell isolation layer and a second cell isolation layer stacked in a direction perpendicular to the lower structure and each including a void… wherein the void, the horizontal layer, and the first and second horizontal conductive lines vertically overlap with each other." However, at the time of the invention, interlayer dielectric (ILD) layers like those claimed were known to include voids. Voids, air gaps, and air spacers were commonly known modifications to ILD layers used to alter their dielectric constant.
At the time of the invention, air gaps or voids were notoriously well-known for the generic purpose of lowering the dielectric constant of the dielectric (such as silicon oxide, as used in Jung et al.). This was done to decrease parasitic capacitance between conductive elements (e.g., word lines and gates).
For support, see Hasnai et al., Figure 14 and paragraph 50, which states: “The described embodiments provide a number of advantages compared to conventional solutions. For example, replacing continuous dielectric layers between wordlines of a memory array with partial dielectric layers, e.g., dielectric layers having an air gap inside them or low-k material disposed inside them, may reduce the overall wordline capacitance. This may improve the memory device performance by reducing the time required to operate the memory device.”
PNG
media_image8.png
396
550
media_image8.png
Greyscale
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the ILD of Jung et al. with a void-containing ILD as disclosed in Hasnai et al. This is because applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to such a person at the time of filing the invention, as established in KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007)
CLAIM 16. Jung et al. in view of Hasnai et al. in view of Kim et al. disclose a semiconductor device of wherein the void capping layer is disposed within the first and second cell isolation layers to cover an opening of the void (Fig. 22a).
CLAIM 17. (New) The semiconductor device of App. No.: 18/460,601 17. (New) The semiconductor device of wherein the void capping layer does not cover the outer wall of the first electrode (Fig. 22a).
CLAIM 18. Jung et al. in view of Hasnai et al. in view of Kim et al. disclose a semiconductor device of claim 15, wherein the void capping layer includes silicon oxide (Jung et al. ¶105 – ILD may be Silicon Oxide.).
Claim(s) 14, 6-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 20210257368 A1) in view of Hasnai et al. (US 20190043882 A1) in view of Kim et al. (US 20200279601 A1).
CLAIM 14. Jung et al. in view of Hasnai et all disclose a semiconductor device of claim 1, however may be silent upon wherein the covered portions have a greater horizontal length than the protruding portions.
At the time of the invention, the specific shape relationship described was a known and capable option. See Kim et al., Figure 5, which depicts an analogous overall device structure of Jung as applied to claim 1. Kim et al. demonstrates that the first electrode of the capacitor may extend a finite distance between the interlayer dielectric (ILD) layers such that the electrode and ILD layers vertically overlap, thereby resulting in the covered portions have a greater horizontal length than the protruding portions.
As demonstrated in Kim et al., the electrode of the capacitor may extend some finite amount toward the semiconductor layer, positioned between the ILD layers on opposing sides of the transistor structure. This simple change in shape was known and used at the time of the invention and is not understood to provide any further unexpected result or benefit; it is, therefore, merely a simple change in shape.
As such, the feature would be recognized as an obvious variant by a person of ordinary skill in the art (POSITA) at the time of filing the invention, as guided by MPEP § 2144.04(a), "Simple Changes in Shape or Size."
PNG
media_image11.png
510
724
media_image11.png
Greyscale
PNG
media_image12.png
252
284
media_image12.png
Greyscale
As demonstrated the electrode of the capacitor may extend toward the semiconductor layer some finite amount between the ILD layers on opposing sides of the transistor structure. This simple change in shape was known and used at the time of the invention and is not understood to provide any further unexpected result or benefit, thereby being a simple change in shape. As such, the feature is recognized as a obvious variant by a POSITA at the time of filing the invention, as provided by the guidance in MPEP 2144.04.
CLAIM 5. Jung et al. in view of Hasnai et al. in view of Kim et al. disclose a semiconductor device of claim 1, wherein the voids, the horizontal layer, and the first and second horizontal conductive lines vertically overlap with each other (As demonstrated in Park et al., the voids occur throughout the ILD layer[s]/material, thus would be expected and understood to be in the recited relative location of the ILD layers as demonstrated in both Jung et al. and Kim et al.).
CLAIM 6. Jung et al. in view of Park et al. in view of Kim et al. disclose a semiconductor device of claim 1, wherein the first and second cell isolation layers include silicon oxide (Jung et al. ¶105 – ILD may be Silicon Oxide.).
CLAIM 7. Jung et al. in view of Park et al. in view of Kim et al. disclose a semiconductor device of claim 1, wherein the first electrode includes an inner wall and a plurality of outer walls, and the outer walls of the first electrode are not covered by the first and second cell isolation layers (Both Jung et al. Fig. 22a & Kim et al. Fig. 5 – Note: This limitation is ambiguous and does not clearly specify which walls are intended to be claimed, as in the inter-digitated cylindrical capacitor structure described and depicted in the claims and prior art have many walls the one could arbitrarily point to.)
CLAIM 8. Jung et al. in view of Hasnai et al. in view of Kim et al. disclose a semiconductor device of claim 1, further comprising: a void capping layer capping the voids of the first and second cell isolation layers
PNG
media_image13.png
484
528
media_image13.png
Greyscale
PNG
media_image14.png
252
284
media_image14.png
Greyscale
CLAIM 9. Jung et al. in view of Hasnai et al. in view of Kim et al. disclose a semiconductor device of claim 8, wherein the void capping layer includes silicon oxide (Jung et al. ¶105 – ILD may be Silicon Oxide.).
CLAIM 10. Jung et al. in view of Hasnai et al. in view of Kim et al. disclose a semiconductor device of claim 1, further comprising: a first contact node between the vertical conductive line and the horizontal layer; and a second contact node between the first electrode of the data storage element and the horizontal layer ("Contact nodes" are understood and expected parts of the circuit. In conventional circuit diagrams, a dot is used to explicitly indicate an electrical connection (node) where lines intersect; the absence of a dot typically means the wires cross without connecting.
The circuit diagram shown in Figure 1 of Jung et al. shows a dot at the intersection of the bit line and the transistor's drain, indicating a connection there. Conversely, it shows no dot (or simply an implied connection due to it being an endpoint of a component) on the line between the capacitor and the source. Nodes are generally understood as the specific points where two or more circuit elements or lines are electrically joined. ).
PNG
media_image15.png
588
560
media_image15.png
Greyscale
CLAIM 11. Jung et al. in view of Hasnai et al. in view of Kim et al. disclose a semiconductor device of claim 10, wherein the first contact node and the second contact node include polysilicon that is doped with an N-type impurity (Jung et al. ¶48 – SP may be polysilicon. ¶55- BL may be polysilicon, ¶81- EL1/EL2 of capacitor may be doped polysilicon The specific choice between N or P doping types is an obvious design choice required for proper circuit function. If the source/drain (S/D) regions of the transistor are N-type, the polysilicon of the corresponding bit line or capacitor electrode would be matched accordingly (i.e., doped N-type) to form appropriate ohmic contacts and junctions. The reverse would be true for a P-type configuration.).
CLAIM 12. Jung et al. in view of Hasnai et al. in view of Kim et al. disclose a semiconductor device of claim 10, wherein the horizontal layer further includes: a first doped region coupled to the first contact node; a second doped region coupled to the second contact node; and a channel between the first doped region and the second doped region (Both Jung fig. 1, 3a &22a; Kim et al. fig. 5 -- It is notoriously well-known in the art that a semiconductor "horizontal layer" includes the first doped source region, the second doped drain region, and the channel situated between them, forming the fundamental structure of a field-effect transistor.)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
3/3/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898