DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 04/14/2026 has been acknowledged. Claims 1 and 11 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because Figure 5 has transistor T7 marked as T4. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application.
Response to Arguments
Applicant’s arguments filed 04/14/2026 with respect to the rejection of claims 1 and 11 have been fully considered but are moot in view of the new grounds of rejection.
Applicant’s arguments filed 04/14/2026 with respect to the rejection of claims 4 and 14 have been fully considered but are moot in view of the new grounds of rejection.
Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Zhang (US 20220199830 A1 – hereinafter Zhang).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-5, 8-10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 20210359066 A1 – hereinafter An) in view of Huang et al. (US 20250089459 A1 – hereinafter Huang), Zhang (US 20220199830 A1 – hereinafter Zhang), and Son et al. (US 20210265449 A1 – hereinafter Son).
Regarding independent claim 1, An teaches
(Currently Amended) A display apparatus ([0019] – “display apparatus”
– hereinafter ‘10’) comprising:
a substrate (100 – Fig. 1 – [0062] – “substrate 100”);
a scan line (SL2 – Fig. 3 – [0069] – “scan line SL2”) disposed over the
substrate (100) and extending in a first direction (x – Fig. 3 – [0071] – “the second scan line SL2 … may extend in a first direction (x)”);
an initialization voltage line (VIL2 – Fig. 3 – [0070] – “second initialization
voltage line VIL2”) disposed over the substrate (100) and extending in the first direction (x – [0071] – “VIL2 may extend in a first direction (x)”);
a first thin-film transistor (T1 – Fig. 4 – [0070] – “first transistor T1”) including a first semiconductor layer (AS1 – Fig. 4 – [0125] – “first semiconductor layer AS1”) and a first gate electrode (G1 – Fig. 4 – [0097] – “first gate electrode G1”) insulated (112 – Fig. 4 – [0097] – “first gate insulating layer 112”) from the first semiconductor layer (AS1 – fig. 4 shows this), the first semiconductor layer (AS1) including a silicon semiconductor ([0104] – “T1, T2, T5, T6, and T7 including the silicon semiconductor”); and
a second thin-film transistor (T7 – Fig. 4 – [0078] – “The seventh transistor T7 may be a second initialization transistor and may be electrically connected to the second scan line SL2, that is, a next scan line, and the second initialization voltage line VIL2”) including a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer including an oxide, wherein
the second semiconductor layer is disposed between the scan line and the initialization voltage line in a plan view,
the second gate electrode extends ([0078] – “The seventh transistor T7 may be turned on according to a second scan signal GP2 that is a next scan signal transferred through the second scan line SL2, and may transfer the second initialization voltage Vint2 from the second initialization voltage line VIL2 to the organic light-emitting diode OLED and to initialize the organic light-emitting diode OLED” – this describes the gate electrode connected to the scan line) from the scan line (SL2) in a second direction (y – Fig. 3 – [0071] – “second direction (y)”) perpendicular to the first direction (x), and
the second semiconductor layer is electrically connected to a light emitting element disposed on the substrate ([0078] – “The seventh transistor T7 may be turned on according to a second scan signal GP2 that is a next scan signal transferred through the second scan line SL2, and may transfer the second initialization voltage Vint2 from the second initialization voltage line VIL2 to the organic light-emitting diode OLED and to initialize the organic light-emitting diode OLED” – this describes the semiconductor layer connected to the OLED).
An does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Huang teaches
a second thin-film transistor (T7 – Fig. 4 – [0121] – “the seventh transistor T7 may each include a bottom gate electrode and a top gate electrode, the bottom gate electrode may be arranged in the first conductive layer, and the top gate electrode may be arranged in the second conductive layer”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, substitute the dual gate transistor structure for the transistor T7, the second initialization transistor as taught by Huang into An.
An ordinary artisan would have been motivated to use the known technique of Huang in the manner set forth above to produce the predictable result of reducing leakage current.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
An and Huang do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Zhang teaches
a second semiconductor layer (2 – Fig. 2 – [0036] – “As shown in FIG. 2, the metal oxide transistor includes a first gate electrode 1, an active layer 2, a second gate electrode 3, and a source-drain electrode 4 that are stacked”) and a second gate electrode (3 – Fig. 2 – [0036] – “As shown in FIG. 2, the metal oxide transistor includes a first gate electrode 1, an active layer 2, a second gate electrode 3, and a source-drain electrode 4 that are stacked”) insulated ([0038] – “the source electrode 5 and the drain electrode 6 are formed after a via is formed on an insulating layer between the source-drain electrode 4 and the active layer 2” – Fig. 2 shows this) from the second semiconductor layer (2), the second semiconductor layer (2) including an oxide semiconductor ([0036] – “The active layer 2 includes a plurality of active sub-layers 7. The active sub-layer 7 includes a metal oxide and has a semiconductor zone 8”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second semiconductor structure as taught by Zhang into An and Huang.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result of reducing leakage current because [0003] – “metal oxide transistors have characteristics of lower leakage current and lower power consumption, and are widely used in various driving circuits.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
An, Huang, and Zhang do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Son teaches
the second semiconductor layer (SC2 – Fig. 4 – [0083] – “second semiconductor layer SC2 may include an oxide semiconductor”) is disposed between the scan line (GL1 – Fig. 4 – [0082] – “scan line GL1”) and the initialization voltage line (VL2 – Fig. 4 – [0082] – “initializing voltage line VL2”) in a plan view (Fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second semiconductor structure as taught by Son into An, Huang, and Zhang.
An ordinary artisan would have been motivated to use the known technique of Son in the manner set forth above to produce the predictable result [0028] – “to prevent deterioration of image quality while increasing resolution.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 2, An, as modified by Huang, Zhang, and Son, teaches claim 1 from which claim 2 depends. An further teaches
(Original) The display apparatus of claim 1, wherein the second
semiconductor layer ([0103] – “seventh transistor T7 may include a seventh semiconductor layer and a seventh gate electrode G7” – hereinafter ‘AO7’) is electrically connected to the initialization voltage line (VIL2 – [0078] – “The seventh transistor T7 may be turned on according to a second scan signal GP2 that is a next scan signal transferred through the second scan line SL2, and may transfer the second initialization voltage Vint2 from the second initialization voltage line VIL2 to the organic light-emitting diode OLED and to initialize the organic light-emitting diode OLED”).
Regarding claim 3, An, as modified by Huang, Zhang, and Son, teaches claim 1 from which claim 3 depends. An further teaches
(Original) The display apparatus of claim 1, wherein a vertical
distance from the substrate (100) to the second semiconductor layer (AO7 – [0125] – “the second semiconductor layer AS2 (not illustrated) of the second transistor T2, the channel region A5, the source region S5, and the drain region D5, that is, a fifth semiconductor layer AS5 of the fifth transistor T5, the channel region A6, the source region S6, and the drain region D6, that is, a sixth semiconductor layer AS6 of the sixth transistor T6, the channel region A7, the source region S7, and the drain region D7, that is, the seventh semiconductor layer of the seventh transistor T7. The channel region, the source region, and the drain region in each of the first, second, and fifth to seventh transistors T1, T2, T5, T6, and T7 may be parts of the semiconductor layer AS” – AO7 is in the same second semiconductor layer as AO4, Fig. 4 shows AO4) is greater than a vertical distance from the substrate (100) to the first semiconductor layer (A1 – Fig. 4 shows this as AO4 for the second semiconductor layer reference).
Regarding claim 4, An, as modified by Huang, Zhang, and Son, teaches claim 1 from which claim 4 depends. An further teaches
(Original) The display apparatus of claim 1, wherein
the second thin-film transistor (T7) further includes a third gate electrode disposed below the second semiconductor layer to overlap the second semiconductor layer, and
the third gate electrode extends from the initialization voltage line (VIL2) in the second direction (y – Fig. 3 shows this).
An, Huang, and Son do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Zhang teaches
the second thin-film transistor further includes a third gate electrode (1 – Fig. 2 – [0100] – “the gate electrode of the second transistor M2 represents the first gate electrode 1 and the second gate electrode 3 of the second transistor M2” – M2 is a dual gate transistor) disposed below the second semiconductor layer (2) to overlap the second semiconductor layer (2 – Fig. 2 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dual gate semiconductor structure as taught by Zhang into An, Huang, and Son.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result of improving control over the channel and improving performance.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 5, An, as modified by Huang, Zhang, and Son, teaches claim 4 from which claim 5 depends. An further teaches
(Original) The display apparatus of claim 4, further comprising:
a first capacitor (Cst – Fig. 4 – [0069] – “first capacitor Cst”) including a lower
electrode (CE1 – Fig. 4 – [0079] – “electrode CE1”) and an upper electrode (CE2 – Fig. 4 – [0079] – “electrode CE2”) over the lower electrode (CE1), wherein
the lower electrode (CE1) and the first gate electrode (G1) are disposed on a same layer (Fig. 4 shows this), and
the upper electrode (CE2) and the third gate electrode (G4a) are disposed on a same layer (Fig. 4 shows this).
Regarding claim 8, An, as modified by Huang, Zhang, and Son, teaches claim 1 from which claim 8 depends. An further teaches
(Original) The display apparatus of claim 1, further comprising:
a third thin-film transistor (T3 – Fig. – [0104] – “T3 and T4 including the oxide
semiconductor”) including a third semiconductor layer (AO3 – Fig. 3 – [0140] – “semiconductor layer AO may include the channel region A3, the source region S3, and the drain region D3, that is, a third semiconductor layer AO3 of the third transistor T3”) and a fourth gate electrode (G3 – [0107] – “third transistor T3 may include a third semiconductor layer including an oxide semiconductor, and a third gate electrode G3”) insulated from the third semiconductor layer (AO3), wherein
the third semiconductor layer (AO3) includes an oxide semiconductor ({[0138] – “semiconductor layer AO including an oxide semiconductor “}, {[0140] – “T3 and T4 may be parts of the semiconductor layer AO”}), and
the third semiconductor layer (AO3) is spaced apart from the second semiconductor layer (AO7) of the second thin-film transistor (T7 – Fig. 3 shows this with A3 and A4 containing AO3 and AO4, AO7 is the same layer as AO4 and spaced apart from AO3).
Regarding claim 9, An, as modified by Huang, Zhang, and Son, teaches claim 8 from which claim 9 depends. An further teaches
(Original) The display apparatus of claim 8, further comprising:
a second capacitor (Cbt – Fig. 4 – [0080] – “second capacitor Cbt”) including a
lower electrode (CE3 – Fig. 4 – [0080] – “electrode CE3”) and an upper electrode (CE4 – Fig. 4 – [0080] – “electrode CE4”), wherein
the lower electrode (CE3) and the first gate electrode (G1) are disposed on a same layer (Fig. 4 shows this), and
the upper electrode (CE4) and the third semiconductor layer (AO3) are disposed on a same layer ([0110] – “electrode CE4 may be disposed at the same layer as that of the third semiconductor layer of the third transistor T3 and the fourth semiconductor layer of the fourth transistor T4”).
Regarding claim 10, An, as modified by Huang, Zhang, and Son, teaches claim 9 from which claim 10 depends. An further teaches
(Original) The display apparatus of claim 9, wherein the upper
electrode (CE4) of the second capacitor (Cbt) extends from the third semiconductor layer ([0110] – “Alternatively, the fourth electrode CE4 may extend from the third semiconductor layer”).
Regarding claim 12, An, as modified by Huang, Zhang, and Son, teaches claim 11 from which claim 12 depends. An, Huang, and Zhang do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Son teaches
(Original) The display apparatus of claim 11, wherein the second
semiconductor layer (SC2 – Fig. 4 – [0083] – “second semiconductor layer SC2 may include an oxide semiconductor”) is disposed between the scan line (GL1 – Fig. 4 – [0082] – “scan line GL1”) and the initialization voltage line (VL2 – Fig. 4 – [0082] – “initializing voltage line VL2”) in a plan view (Fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second semiconductor structure as taught by Son into An, Huang, and Zhang.
An ordinary artisan would have been motivated to use the known technique of Son in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Huang, Zhang, Son and Kim et al. (US 20170249896 A1 – hereinafter Kim).
Regarding claim 6 , An, as modified by Huang, Zhang, and Son, teaches claim 1 from which claim 6 depends. An further teaches
(Original) The display apparatus of claim 1, further comprising:
an emission control line (EL – Fig. 3 – [0069] – “emission control line EL”)
spaced apart from the initialization voltage line (VIL2) and extending in the first direction (x – Fig. 3 shows this).
An, Huang, Zhang, and Son, do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Kim teaches
wherein
the emission control line (E2i – [0190] – “emitting control line E2i”) overlaps ([0190] – “second scan lines S2i−1, S2i and S2i+1 overlap the second light emitting control line E2i”) the scan line (S2i – [0190] – “scan lines S2i−1, S2i and S2i+1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the emission control and scan line overlap structure as taught by Kim into An, Huang, Zhang, and Son.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0005] – “a display device having a uniform brightness across a display area of the display device” by limiting the area obstructed by the lines.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 7 , An, as modified by Huang, Zhang, Son and Kim, teaches claim 6 from which claim 7 depends. An further teaches
(Original) The display apparatus of claim 6, wherein the emission
control line (EL) and the first gate electrode (G1) are disposed on a same layer ([0013] – “the emission control line 135 may be disposed at the same layer as that of the first gate electrode G1”).
Claims 11, 13-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Huang and Zhang.
Regarding independent claim 11, An teaches
(Currently Amended) A display apparatus ([0019] – “display apparatus”
– hereinafter ‘10’) comprising:
a substrate (100 – Fig. – [0062] – “substrate 100”);
a scan line (SL2 – Fig. 3 – [0069] – “scan line SL2”) disposed over the
substrate (100) and extending in a first direction (x – Fig. 3 – [0071] – “the second scan line SL2 … may extend in a first direction (x)”);
an initialization voltage line (VIL2 – Fig. 3 – [0070] – “second initialization
voltage line VIL2”) disposed over the substrate (100) and extending in the first direction (x – [0071] – “VIL2 may extend in a first direction (x)”);
a first thin-film transistor (T1 – Fig. 4 – [0070] – “first transistor T1”) disposed over the substrate (100) and including a first semiconductor layer (AS1 – Fig. 4 – [0125] – “first semiconductor layer AS1”) and a first gate electrode (G1 – Fig. 4 – [0097] – “first gate electrode G1”) insulated (112 – Fig. 4 – [0097] – “first gate insulating layer 112”) from the first semiconductor layer (AS1 – fig. 4 shows this), the first semiconductor layer (AS1) including a silicon semiconductor ([0104] – “T1, T2, T5, T6, and T7 including the silicon semiconductor”); and
a second thin-film transistor (T7 – Fig. 4 – [0078] – “The seventh transistor T7 may be a second initialization transistor and may be electrically connected to the second scan line SL2, that is, a next scan line, and the second initialization voltage line VIL2”) including a second semiconductor layer, and a third gate electrode, the second semiconductor layer including an oxide semiconductor, the second gate electrode disposed over the second semiconductor layer, the third gate electrode overlapping the second gate electrode and disposed below the second semiconductor layer,
wherein the third gate electrode extends from the initialization voltage line (VIL2) in a second direction (y – Fig. 3 – [0071] – “second direction (y)”) perpendicular to the first direction (x),
the third gate electrode is electrically disconnected from the second gate electrode, and
the second semiconductor layer overlaps each of the second gate electrode and the third gate electrode.
An does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Huang teaches
a second thin-film transistor (T7 – Fig. 4 – [0121] – “the seventh transistor T7 may each include a bottom gate electrode and a top gate electrode, the bottom gate electrode may be arranged in the first conductive layer, and the top gate electrode may be arranged in the second conductive layer”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, substitute the dual gate transistor structure for the transistor T7, the second initialization transistor as taught by Huang into An.
An ordinary artisan would have been motivated to use the known technique of Huang in the manner set forth above to produce the predictable result of reducing leakage current.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
An and Huang do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Zhang teaches
a second semiconductor layer (2 – Fig. 2 – [0036] – “As shown in FIG. 2, the metal oxide transistor includes a first gate electrode 1, an active layer 2, a second gate electrode 3, and a source-drain electrode 4 that are stacked”), and a third gate electrode (1 – Fig. 2 – [0100] – “the gate electrode of the second transistor M2 represents the first gate electrode 1 and the second gate electrode 3 of the second transistor M2” – M2 is a dual gate transistor), the second semiconductor layer (2 – Fig. 2 – [0036] – “As shown in FIG. 2, the metal oxide transistor includes a first gate electrode 1, an active layer 2, a second gate electrode 3, and a source-drain electrode 4 that are stacked”) including an oxide semiconductor ([0036] – “As shown in FIG. 2, the metal oxide transistor includes a first gate electrode 1, an active layer 2, a second gate electrode 3, and a source-drain electrode 4 that are stacked” – element 2 is an oxide due to the transistor being a metal oxide transistor), the second gate electrode (3 – Fig. 2 – [0036] – “As shown in FIG. 2, the metal oxide transistor includes a first gate electrode 1, an active layer 2, a second gate electrode 3, and a source-drain electrode 4 that are stacked”) disposed over the second semiconductor layer (2 – Fig. 2 shows this), the third gate electrode (1) overlapping the second gate electrode (3) and disposed below the second semiconductor layer (2 – Fig. 2 shows this),
the third gate electrode (1) is electrically disconnected from the second gate electrode (3 – Fig. 2 shows this), and
the second semiconductor (2) layer overlaps each of the second gate electrode (3) and the third gate electrode (1 – Fig. 2 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second semiconductor structure as taught by Zhang into An and Huang.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result of reducing leakage current because [0003] – “metal oxide transistors have characteristics of lower leakage current and lower power consumption, and are widely used in various driving circuits.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 13 , An, as modified by Huang and Zhang, teaches claim 11 from which claim 13 depends. An further teaches
(Original) The display apparatus of claim 11, wherein
the second semiconductor layer ([0103] – “seventh transistor T7 may include a seventh semiconductor layer and a seventh gate electrode G7” – hereinafter ‘AO7’) is electrically connected to the initialization voltage line (VIL2 – [0078] – “The seventh transistor T7 may be turned on according to a second scan signal GP2 that is a next scan signal transferred through the second scan line SL2, and may transfer the second initialization voltage Vint2 from the second initialization voltage line VIL2 to the organic light-emitting diode OLED and to initialize the organic light-emitting diode OLED”).
Regarding claim 14 , An, as modified by Huang and Zhang, teaches claim 11 from which claim 14 depends. An further teaches
(Original) The display apparatus of claim 11, wherein the second gate
electrode extends from the scan line (SL2) in the second direction (y – Fig. 3 shows this).
An and Huang do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Zhang teaches
the second gate electrode (3).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second semiconductor structure as taught by Zhang into An and Huang.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result as stated above in claim 11.
Regarding claim 15 , An, as modified by Huang and Zhang, teaches claim 11 from which claim 15 depends. An further teaches
(Original) The display apparatus of claim 11, further comprising:
a first capacitor (Cst – Fig. 4 – [0069] – “first capacitor Cst”) including a lower
electrode (CE1 – Fig. 4 – [0079] – “electrode CE1”) and an upper electrode (CE2 – Fig. 4 – [0079] – “electrode CE2”) over the lower electrode (CE1), wherein
the lower electrode (CE1) and the first gate electrode (G1) are disposed on
a same layer (Fig. 4 shows this), and
the upper electrode (CE2) and the third gate electrode (G4a) are disposed
on a same layer (Fig. 4 shows this).
Regarding claim 18 , An, as modified by Huang and Zhang, teaches claim 11 from which claim 18 depends. An further teaches
(Original) The display apparatus of claim 11, further comprising:
a third thin-film transistor (T3 – Fig. – [0104] – “T3 and T4 including the oxide
semiconductor”) including a third semiconductor layer (AO3 – Fig. 3 – [0140] – “semiconductor layer AO may include the channel region A3, the source region S3, and the drain region D3, that is, a third semiconductor layer AO3 of the third transistor T3”) and a fourth gate electrode (an (G3 – [0107] – “third transistor T3 may include a third semiconductor layer including an oxide semiconductor, and a third gate electrode G3”) insulated from the third semiconductor layer, wherein
the third semiconductor layer (AO3) includes an oxide semiconductor ({[0138] – “semiconductor layer AO including an oxide semiconductor “}, {[0140] – “T3 and T4 may be parts of the semiconductor layer AO”}), and
the third semiconductor layer (AO3) is spaced apart from the second semiconductor layer (AO4) of the second thin-film transistor (T4 – Fig. 3 shows this with A3 and A4 containing AO3 and AO4).
Regarding claim 19 , An, as modified by Huang and Zhang, teaches claim 18 from which claim 19 depends. An further teaches
(Original) The display apparatus of claim 18, further comprising:
a second capacitor (Cbt – Fig. 4 – [0080] – “second capacitor Cbt”) including a
lower electrode (CE3 – Fig. 4 – [0080] – “electrode CE3”) and an upper electrode (CE4 – Fig. 4 – [0080] – “electrode CE4”), wherein
the lower electrode (CE3) and the first gate electrode (G1) are disposed on a same layer (Fig. 4 shows this), and
the upper electrode (CE4) and the third semiconductor layer (AO3) are disposed on a same layer ([0110] – “electrode CE4 may be disposed at the same layer as that of the third semiconductor layer of the third transistor T3 and the fourth semiconductor layer of the fourth transistor T4”).
Regarding claim 20 , An, as modified by Huang and Zhang, teaches claim 19 from which claim 20 depends. An further teaches
(Original) The display apparatus of claim 19, wherein the upper
electrode (CE4) of the second capacitor (Cbt) extends from the third semiconductor layer ([0110] – “Alternatively, the fourth electrode CE4 may extend from the third semiconductor layer”).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Huang, Zhang, and Kim.
Regarding claim 16 , An, as modified by Huang and Zhang, teaches claim 11 from which claim 16 depends. An further teaches
(Original) The display apparatus of claim 11, further comprising:
an emission control line (EL – Fig. 3 – [0069] – “emission control line EL”)
spaced apart from the initialization voltage line (VIL2) and extending in the first direction (x – Fig. 3 shows this).
An, Huang and Zhang do not expressly disclose the other limitations of claim 16.
However, in an analogous art, Kim teaches
wherein
the emission control line (E2i – [0190] – “emitting control line E2i”) overlaps ([0190] – “second scan lines S2i−1, S2i and S2i+1 overlap the second light emitting control line E2i”) the scan line (S2i – [0190] – “scan lines S2i−1, S2i and S2i+1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the emission control and scan line overlap structure as taught by Kim into An, Huang, and Zhang.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0005] – “a display device having a uniform brightness across a display area of the display device” by limiting the area obstructed by the lines.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 17 , An, as modified by Huang, Zhang, and Kim, teaches claim 16 from which claim 17 depends. An further teaches
(Original) The display apparatus of claim 16, wherein the emission
control line (EL) and the first gate electrode (G1) is disposed on a same layer ([0013] – “the emission control line 135 may be disposed at the same layer as that of the first gate electrode G1”).
Pertinent Art
For the benefits of the Applicant, US 20190252479 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including “the emission control line overlaps the scan line”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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