DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
The following is a quotation of 35 U.S.C. 102(a)(2) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claim 1-5, 8-15, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being
anticipated by An et al. (US 20210359066 A1 – hereinafter An).
Regarding independent claim 1, An teaches:
A display apparatus ([0019] – “display apparatus” – hereinafter ‘10’)
comprising:
a substrate (100 – Fig. – [0062] – “substrate 100”);
a scan line (SL4 – Fig. 3 – [0069] – “scan line SL4”) disposed over the
substrate (100) and extending in a first direction (x – Fig. 3 – [0071] – “first direction (x)”);
an initialization voltage line (VIL1 – Fig. 3 – [0070] – “initialization voltage line
VIL1”) disposed over the substrate (100) and extending in the first direction (x);
a first thin-film transistor (T1 – Fig. 4 – [0070] – “first transistor T1”) including a first semiconductor layer (AS1 – Fig. 4 – [0125] – “first semiconductor layer AS1”) and a first gate electrode (G1 – Fig. 4 – [0097] – “first gate electrode G1”) insulated (112 – Fig. 4 – [0097] – “first gate insulating layer 112”) from the first semiconductor layer (AS1 – fig. 4 shows this), the first semiconductor layer (AS1) including a silicon semiconductor ([0104] – “T1, T2, T5, T6, and T7 including the silicon semiconductor”); and
a second thin-film transistor (T4 – Fig. 4 – [0108] – “transistor T4”) including a second semiconductor layer (AO4 – Fig. 4 – [0140] – “fourth semiconductor layer AO4 of the fourth transistor T4”) and a second gate electrode (G4b – Fig. 4 – [0108] – “gate electrode G4b”) insulated (115 – fig. 4 – [0109] – “gate insulating layer 115”) from the second semiconductor layer (AO4), the second semiconductor layer (AO4) including an oxide semiconductor ({[0138] – “semiconductor layer AO including an oxide semiconductor “}, {[0140] – “T3 and T4 may be parts of the semiconductor layer AO”}), wherein
the second semiconductor layer (AO4) is disposed between the scan line (SL4) and the initialization voltage line (VIL1) in a plan view (Fig. 3 shows this), and
the second gate electrode (G4) extends from the scan line (SL4) in a second direction (y – Fig. 3 – [0071] – “second direction (y)”) perpendicular to the first direction (x).
Regarding claim 2, An teaches claim 1 from which claim 2 depends. An further teaches
wherein the second semiconductor layer (AO4) is electrically
connected to the initialization voltage line (VIL1 – [0069] – “pixel circuit PC may be electrically connected to signal lines, first and second initialization voltage lines VIL1” – A4 is the semiconductor layer of T1 which is the driving transistor of the pixel circuit, therefore they are connected).
Regarding claim 3, An teaches claim 1 from which claim 3 depends. An further teaches
wherein a vertical distance from the substrate (100) to the second
semiconductor layer (AO4) is greater than a vertical distance from the substrate (100) to the first semiconductor layer (A1 – Fig. 4 shows this).
Regarding claim 4, An teaches claim 1 from which claim 4 depends. An further teaches
wherein
the second thin-film transistor (T4) further includes a third gate electrode
(G4a – Fig. 4 – [0136] – “a portion overlapping a semiconductor layer AO may be a lower gate electrode G4a of the fourth transistor T4”) disposed below the second semiconductor layer (AO4) to overlap the second semiconductor layer (AO4), and
the third gate electrode (G4a) extends from the initialization voltage line (VIL1) in the second direction (y – Fig. 3 shows this).
Regarding claim 5, An teaches claim 4 from which claim 5 depends. An further teaches
further comprising:
a first capacitor (Cst – Fig. 4 – [0069] – “first capacitor Cst”) including a lower
electrode (CE1 – Fig. 4 – [0079] – “electrode CE1”) and an upper electrode (CE2 – Fig. 4 – [0079] – “electrode CE2”) over the lower electrode (CE1), wherein
the lower electrode (CE1) and the first gate electrode (G1) are disposed on a same layer (Fig. 4 shows this), and
the upper electrode (CE2) and the third gate electrode (G4a) are disposed on a same layer (Fig. 4 shows this).
Regarding claim 8, An teaches claim 1 from which claim 8 depends. An further teaches
further comprising:
a third thin-film transistor (T3 – Fig. – [0104] – “T3 and T4 including the oxide
semiconductor”) including a third semiconductor layer (AO3 – Fig. 3 – [0140] – “semiconductor layer AO may include the channel region A3, the source region S3, and the drain region D3, that is, a third semiconductor layer AO3 of the third transistor T3”) and a fourth gate electrode (G3 – [0107] – “third transistor T3 may include a third semiconductor layer including an oxide semiconductor, and a third gate electrode G3”) insulated from the third semiconductor layer (AO3), wherein
the third semiconductor layer (AO3) includes an oxide semiconductor ({[0138] – “semiconductor layer AO including an oxide semiconductor “}, {[0140] – “T3 and T4 may be parts of the semiconductor layer AO”}), and
the third semiconductor layer (AO3) is spaced apart from the second semiconductor layer (AO4) of the second thin-film transistor (T4 – Fig. 3 shows this with A3 and A4 containing AO3 and AO4).
Regarding claim 9, An teaches claim 8 from which claim 9 depends. An further teaches
further comprising:
a second capacitor (Cbt – Fig. 4 – [0080] – “second capacitor Cbt”) including a
lower electrode (CE3 – Fig. 4 – [0080] – “electrode CE3”) and an upper electrode (CE4 – Fig. 4 – [0080] – “electrode CE4”), wherein
the lower electrode (CE3) and the first gate electrode (G1) are disposed on a same layer (Fig. 4 shows this), and
the upper electrode (CE4) and the third semiconductor layer (AO3) are disposed on a same layer ([0110] – “electrode CE4 may be disposed at the same layer as that of the third semiconductor layer of the third transistor T3 and the fourth semiconductor layer of the fourth transistor T4”).
Regarding claim 10, An teaches claim 9 from which claim 10 depends. An further teaches
wherein the upper electrode (CE4) of the second capacitor (Cbt)
extends from the third semiconductor layer ([0110] – “Alternatively, the fourth electrode CE4 may extend from the third semiconductor layer”).
Regarding independent claim 11, An teaches:
A display apparatus (an ([0019] – “display apparatus” – hereinafter ‘10’)
comprising:
a substrate (100 – Fig. – [0062] – “substrate 100”);
a scan line (SL4 – Fig. 3 – [0069] – “scan line SL4”) disposed over the
substrate (100) and extending in a first direction (x – Fig. 3 – [0071] – “first direction (x)”);
an initialization voltage line (VIL1 – Fig. 3 – [0070] – “initialization voltage line
VIL1”) disposed over the substrate (100) and extending in the first direction (x);
a first thin-film transistor (T1 – Fig. 4 – [0070] – “first transistor T1”) disposed over the substrate (100) and including a first semiconductor layer (AS1 – Fig. 4 – [0125] – “first semiconductor layer AS1”) and a first gate electrode (G1 – Fig. 4 – [0097] – “first gate electrode G1”) insulated (112 – Fig. 4 – [0097] – “first gate insulating layer 112”) from the first semiconductor layer (AS1 – fig. 4 shows this), the first semiconductor layer (AS1) including a silicon semiconductor ([0104] – “T1, T2, T5, T6, and T7 including the silicon semiconductor”); and
a second thin-film transistor (T4 – Fig. 4 – [0108] – “transistor T4”) including a second semiconductor layer (AO4 – Fig. 4 – [0140] – “fourth semiconductor layer AO4 of the fourth transistor T4”), a second gate electrode (G4b – Fig. 4 – [0144] – “gate electrode G4b of the fourth transistor T4”), and a third gate electrode (G4a – Fig. 4 – [0136] – “a portion overlapping a semiconductor layer AO may be a lower gate electrode G4a of the fourth transistor T4”), the second semiconductor layer (AO4) including an oxide semiconductor ({[0138] – “semiconductor layer AO including an oxide semiconductor “}, {[0140] – “T3 and T4 may be parts of the semiconductor layer AO”}), the second gate electrode (G4b) disposed over the second semiconductor layer (AO4 – fig 4 shows this), the third gate electrode (G4a) overlapping the second gate electrode (G4b) and disposed below the second semiconductor layer (AO4 – Fig. 4 shows this),
wherein the third gate electrode (G4a) extends from the initialization voltage line (VIL1) in a second direction (y – Fig. 3 – [0071] – “second direction (y)”) perpendicular to the first direction (x).
Regarding claim 12 , An teaches claim 11 from which claim 12 depends. An further teaches
wherein the second semiconductor layer (AO4) is disposed between
the scan line (SL4) and the initialization voltage line (VIL1) in a plan view (Fig. 3 shows this).
Regarding claim 13 , An teaches claim 11 from which claim 13 depends. An further teaches
wherein
the second semiconductor layer (AO4) is electrically connected to the
initialization voltage line (VIL1 – [0069] – “pixel circuit PC may be electrically connected to signal lines, first and second initialization voltage lines VIL1” – A4 is the semiconductor layer of T1 which is the driving transistor of the pixel circuit, therefore they are connected).
Regarding claim 14 , An teaches claim 11 from which claim 14 depends. An further teaches
wherein the second gate electrode (G4b) extends from the scan line
(SL4) in the second direction (y – Fig. 3 shows this).
Regarding claim 15 , An teaches claim 11 from which claim 15 depends. An further teaches
further comprising:
a first capacitor (Cst – Fig. 4 – [0069] – “first capacitor Cst”) including a lower
electrode (CE1 – Fig. 4 – [0079] – “electrode CE1”) and an upper electrode (CE2 – Fig. 4 – [0079] – “electrode CE2”) over the lower electrode (CE1), wherein
the lower electrode (CE1) and the first gate electrode (G1) are disposed on
a same layer (Fig. 4 shows this), and
the upper electrode (CE2) and the third gate electrode (G4a) are disposed
on a same layer (Fig. 4 shows this).
Regarding claim 18 , An teaches claim 11 from which claim 18 depends. An further teaches
further comprising:
a third thin-film transistor (T3 – Fig. – [0104] – “T3 and T4 including the oxide
semiconductor”) including a third semiconductor layer (AO3 – Fig. 3 – [0140] – “semiconductor layer AO may include the channel region A3, the source region S3, and the drain region D3, that is, a third semiconductor layer AO3 of the third transistor T3”) and a fourth gate electrode (G3 – [0107] – “third transistor T3 may include a third semiconductor layer including an oxide semiconductor, and a third gate electrode G3”) insulated from the third semiconductor layer, wherein
the third semiconductor layer (AO3) includes an oxide semiconductor ({[0138] – “semiconductor layer AO including an oxide semiconductor “}, {[0140] – “T3 and T4 may be parts of the semiconductor layer AO”}), and
the third semiconductor layer (AO3) is spaced apart from the second semiconductor layer (AO4) of the second thin-film transistor (T4 – Fig. 3 shows this with A3 and A4 containing AO3 and AO4).
Regarding claim 19 , An teaches claim 18 from which claim 19 depends. An further teaches
further comprising:
a second capacitor (Cbt – Fig. 4 – [0080] – “second capacitor Cbt”) including a
lower electrode (CE3 – Fig. 4 – [0080] – “electrode CE3”) and an upper electrode (CE4 – Fig. 4 – [0080] – “electrode CE4”), wherein
the lower electrode (CE3) and the first gate electrode (G1) are disposed on a same layer (Fig. 4 shows this), and
the upper electrode (CE4) and the third semiconductor layer (AO3) are disposed on a same layer ([0110] – “electrode CE4 may be disposed at the same layer as that of the third semiconductor layer of the third transistor T3 and the fourth semiconductor layer of the fourth transistor T4”).
Regarding claim 20 , An teaches claim 19 from which claim 20 depends. An further teaches
wherein the upper electrode (CE4) of the second capacitor (Cbt)
extends from the third semiconductor layer ([0110] – “Alternatively, the fourth electrode CE4 may extend from the third semiconductor layer”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 6, 7, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Kim et al. (US 20170249896 A1 – hereinafter Kim).
Regarding claim 6 , An teaches claim 1 from which claim 6 depends. An further teaches
further comprising:
an emission control line (EL – Fig. 3 – [0069] – “emission control line EL”)
spaced apart from the initialization voltage line (VIL1) and extending in the first direction (x – Fig. 3 shows this).
An does not expressly disclose the other limitations of claim 6.
However, in an analogous art, Kim teaches
wherein
the emission control line (E2i – [0190] – “emitting control line E2i”) overlaps ([0190] – “second scan lines S2i−1, S2i and S2i+1 overlap the second light emitting control line E2i”) the scan line (S2i – [0190] – “scan lines S2i−1, S2i and S2i+1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the emission control and scan line overlap structure as taught by Kim into An.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0005] – “a display device having a uniform brightness across a display area of the display device” by limiting the area obstructed by the lines.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 7 , An, as modified by Kim, teaches claim 6 from which claim 7 depends. An further teaches
wherein the emission control line (EL) and the first gate electrode
(G1) are disposed on a same layer ([0013] – “the emission control line 135 may be disposed at the same layer as that of the first gate electrode G1”).
Regarding claim 16 , An teaches claim 11 from which claim 16 depends. An further teaches
further comprising:
an emission control line (EL – Fig. 3 – [0069] – “emission control line EL”)
spaced apart from the initialization voltage line (VIL1) and extending in the first direction (x – Fig. 3 shows this).
An does not expressly disclose the other limitations of claim 16.
However, in an analogous art, Kim teaches
wherein
the emission control line (E2i – [0190] – “emitting control line E2i”) overlaps ([0190] – “second scan lines S2i−1, S2i and S2i+1 overlap the second light emitting control line E2i”) the scan line (S2i – [0190] – “scan lines S2i−1, S2i and S2i+1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the emission control and scan line overlap structure as taught by Kim into An.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0005] – “a display device having a uniform brightness across a display area of the display device” by limiting the area obstructed by the lines.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 17 , An, as modified by Kim, teaches claim 16 from which claim 17 depends. An further teaches
wherein the emission control line (EL) and the first gate electrode
(G1) is disposed on a same layer ([0013] – “the emission control line 135 may be disposed at the same layer as that of the first gate electrode G1”).
Pertinent Art
For the benefits of the Applicant, US 20190252479 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including “the emission control line overlaps the scan line”.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897
/GRA/
Examiner, Art Unit 2897