DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 1 in the reply filed on 2/4/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, 9-10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Liebmann et al (US 2022/0181300).
1. A semiconductor package comprising:
a first semiconductor chip (Fig.1 (111/110) and [0023- tiers are chips- see also 0034- which explicitly teaches the tiers are chips]) including a first signal wiring structure (Fig.1 (115) and [0025]) forming a first surface (top) thereof, and a first power wiring structure (Fig.1 (113/114/112) and [0024-all power wirings]) forming a second surface (bottom) thereof, wherein the second surface (bottom) is opposite the first surface (top);
a second semiconductor chip (Fig.1 (121/120) and [0028- tiers are chips- see also 0034- teaching tiers are chips]) disposed on the first signal wiring structure (Fig.1 (115) and [0025]) and including a second signal wiring structure (Fig.1 (125) and [0026]);
a second power wiring structure (Fig.1 (123/124/122) and [0029-all power wirings]) disposed on the second semiconductor chip (Fig.1 (121/120) and [0028]); and
a first power connection pillar (Fig.1 (132) and [0031]) electrically connecting the first power wiring structure (Fig.1 (113) and [0024]) to the second power wiring structure (Fig.1 (123) and [0029]).
2. The semiconductor package of claim 1, further comprising a power wiring substrate (Fig.1 (123) and [0029]) disposed on the second power wiring structure (Fig.1 (124/122) and [0029]).
3. The semiconductor package of claim 1, wherein the first semiconductor chip (Fig.1 (111/110) and [0023]) further includes a first through-via (Fig.1 (114/132) and [0024]) electrically connected to the first signal wiring structure (Fig.1 (115) and [0025/ 0031-connected to signal wiring]) and the first power wiring structure (Fig.1 (113/114/112) and [0024]), wherein the second semiconductor chip (Fig.1 (121/120) and [0028]) further includes a second through-via (Fig.1 (124/131) and [0029]) connected to the second signal wiring structure (Fig.1 (125) and [0026/0031-connected to signal wiring]) and the second power wiring structure (Fig.1 (123/124/122) and [0029]).
5. The semiconductor package of claim 1, wherein a width of the second signal wiring (Fig.1 (125/1251) and [0025-0026]) structure is smaller than a width of the first signal wiring structure (Fig.1 (115/1153) and [0025]) (Fig.1 shows 1251 is smaller in width than 1153).
6. The semiconductor package of claim 1, wherein a width of the second signal wiring structure (Fig.1 (125/1251) and [0025-0026]) is smaller than a width of the second power wiring structure (Fig.1 (123) and [0029]) (Fig.1 shows 1251 is smaller in width than 123).
7. The semiconductor package of claim 1, wherein an upper surface of the first power connection pillar (Fig.1 (132) and [0031]) is in electrical contact with a lower surface of the second power wiring structure (Fig.1 (123) and [0029]), wherein a lower surface of the first power connection pillar (Fig.1 (132) and [0031]) is in contact with an upper surface of the first power wiring structure (Fig.1 (113) and [0024]).
9. The semiconductor package of claim 1, wherein the first power connection pillar (Fig.1 (132) and [0031]) extends through the first signal wiring structure (Fig.1 (115) and [0025]).
10. The semiconductor package of claim 1, wherein the first power connection pillar (Fig.1 (132) and [0031]) is spaced apart from the second semiconductor chip (Fig.1 (121/120) and [0028]) in a first direction (x-direction) and extends in a second direction (y-direction) intersecting the first direction (x/y intersect).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann et al (US 2022/0181300) in further view of Ide (US 2013/0228898)
In reference to claim 4:
Liebmann teaches the limitations of claim 1 as cited above, and further teaches in reference to claim 4:
4. The semiconductor package of claim 1, further comprising the second power wiring structure (Fig.1 (123/124/122) and [0029]) and the first signal wiring structure (Fig.1 (115) and [0025]),, the second semiconductor chip (Fig.1 (121/120) and [0028]), and wherein the first power connection pillar (Fig.1 (132) and [0031]) .
However Liebmann fails to explicitly teach the molding film as bolded below and required by claim 4:
4. The semiconductor package of claim 1, further comprising a molding film disposed between
the second power wiring structure (Fig.1 (123/124/122) and [0029]) and the first signal wiring structure (Fig.1 (115) and [0025]), wherein the molding film surrounds the second semiconductor chip (Fig.1 (121/120) and [0028]), and wherein the first power connection pillar (Fig.1 (132) and [0031])the second power wiring structure and the first signal wiring structure, wherein the molding film (Fig.1 (94) and [0038]) surrounds the second semiconductor chip (Fig.1 (CC2) and [0038]), and wherein the first power connection pillar (Fig.1 (132) and [0031]) extends through the molding film.
However, Ide teaches the molding film as cited below:
4. The semiconductor package of claim 1, further comprising a molding film (Fig.1 (94/96) and [0038]) disposed between wiring layers (Fig.1 (94/96) and [0038]) surrounds the second semiconductor chip (Fig.1 (CC2) and [0038]).
It would have been obvious to one of ordinary skill in the art to modify Liebmann’s teachings to include the underfill/molding layers as taught by Ide (Fig.1 (94/96) and [0038]) because as Ide teaches adding an underfill/molding layer to chip stacks protects the chips within the chip stack [0038]. Moreover,k the use of molding materials is well known and considered conventional in the art.
In reference to claim 8, Liebmann teaches the limitations of claim 1 as cited above; and teaches the following cited limitations of claim 8 as recited below:
8. The semiconductor package of claim 1, the second surface (bottom) of the first semiconductor chip (Fig.1 (111/110) and [0023]) and electrically connected to the first power wiring structure (Fig.1 (113/114/112) and [0024]).
However Liebmann fails to teach the additional limitations of claim 8, bolded below:
8. The semiconductor package of claim 1, further comprising an outer bump on the second surface (bottom) of the first semiconductor chip (Fig.1 (111/110) and [0023]) and electrically connected to the first power wiring structure (Fig.1 (113/114/112) and [0024]).
However, Ide teaches :
8. The semiconductor package of claim 1, further comprising an outer bump (Fig. 1 (91) and [0068]) on the second surface of the first semiconductor chip (Fig.1 (IF) and [0068]) and electrically connected to the first power wiring structure (Fig.1 (TSVv1/v2) and [0068]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Liebmann’s teachings to include a bump connection underlying the first chip to facilitate electrical connection as taught by Ide (Fig. 1 (91) and [0068]) because as Ide teaches, the bumps are suitable for electrical power connectivity [0068]. Moreover bumps are considered to be well known and conventional in the art to electrically and structurally attach packages of stacked chips to underlying circuit boards.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chung et al (US 20240222273); Kang et al (US 2018/0358328); and Yang (US 20250014985) teach similar chip stacks with PDNs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
4/10/26
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