Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/461,086 filed on 09/05/2023.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-8) in the reply filed on 01/07/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over US Pat # 6,509,232 to Kim et al. (Kim) in view of US Pub # 2014/0349464 to Yang et al (Yang).
Regarding independent claim 1, Kim discloses an apparatus comprising:
a first semiconductor substrate (Fig. 32: 302);
a plurality of first regions (Fig. 32) extending in parallel in a first direction on the first semiconductor substrate (302), each of the plurality of first regions including a plurality of first shallow trench isolations (STI) (Fig. 32: 360) therein; and
a plurality of second regions (Fig. 32) each extending between corresponding adjacent two of the plurality of first regions, each of the plurality of second regions including a plurality of second STIs (Fig. 32: 362) and a plurality of active regions (active regions are where 432 are formed, see Fig. 32) arranged alternately and in line in the first direction.
Kim fails to explicitly disclose a greater depth than each of the plurality of first STIs.
Yang discloses wherein a greater depth than each of the plurality of first STIs (Fig. 3F).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the shallow trench isolations (STI) of Kim to includes STI regions having different depth as taught by Yang to improve the trench etching process and prevent local thickness loss of the hard mask layer during the etching process, thereby improving process reliability and isolation formation (¶0063).
Regarding claim 2, Kim discloses a plurality of word-lines (Fig. 3 and corresponding text) extending in a second direction crossing the first direction above the first semiconductor substrate.
Regarding claim 4, Kim discloses wherein the plurality of first STIs (360) and the plurality of second STIs (362) comprise a same material (col. 7, lines 11-16).
Regarding claim 5, Kim discloses wherein the same material comprises silicon dioxide (col. 7, lines 11-16).
Regarding claim 6, Kim discloses a semiconductor apparatus including a semiconductor substrate (302) having a plurality of active regions defined between shallow trench isolation (STI) regions (362) (see Kim, Fig. 32). Kim further teaches a plurality of word-lines (202, 204) extending across the semiconductor substrate (see Kim, Fig. 3). As shown in Fig. 3, the plurality of word-lines extend in a direction crossing the active regions defined between the STI regions of Fig. 32. Each crossing of a word-line over an active region forms a transistor structure in the semiconductor substrate (see Kim, Fig. 32). Accordingly, the word-lines of Kim cross the active regions such that the active regions include transistor structures formed at the intersections.
Because a plurality of word-lines extend across the substrate, each of the active regions is crossed by corresponding ones of the plurality of word-lines, and crossings of the word-lines over the active regions form transistors therein. Thus, Kim teaches the limitation that each of the plurality of active regions is crossed by corresponding word-lines such that each active region comprises transistors, as recited in claim 6.
Regarding claim 7, Kim discloses wherein the plurality of word-lines comprise conductive material.
Kim teaches a plurality of word-lines (202, 204) extending across the semiconductor substrate (see Kim, Fig. 3). However, Kim does not explicitly disclose that the word-lines comprise conductive material. Nevertheless, one of ordinary skill in the art would understand that word-lines in semiconductor memory devices function as gate electrodes used to apply a control voltage to the channel region of the underlying transistors. Gate electrodes must be formed from conductive materials in order to transmit the control voltage used to operate the transistors. Accordingly, it would have been obvious to one of ordinary skill in the art that the word-lines of Kim comprise conductive material.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US Pat # 6,509,232 to Kim et al. (Kim) in view of US Pub # 2014/0349464 to Yang et al (Yang) and further in view of US Pat 5,882,987 to Srikrishnan.
Regarding claim 3, Kim and Yang disclose all of the limitations of claim 2 from which this claim depends.
Kim teaches an insulating film (Fig. 32: 324) associated with the STI structures, which function as an insulating film within the device structure. Kim further shows that the STI regions are positioned between the word-line structures and the semiconductor substrate (see Fig. 32), thereby teaching that the STI regions are sandwiched between the word-lines and the semiconductor substrate.
Kim and Yang fail to discloses a second semiconductor substrate provided on a back surface of the first semiconductor substrate.
Srikrishnan teaches forming semiconductor structures by bonding a first semiconductor wafer (200) to a second wafer (220) through an insulating layer (205 or 207), thereby providing a second semiconductor substrate on the backside of the first semiconductor substrate (col. 2, lines 7-15 and lines 28-40).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to provide the device of Kim with a second semiconductor substrate as taught by Srikrishnan so as to act as a stiffener and provides the bulk silicon under the buried oxide in the SOI structure and to provide structural support during fabrication and enable processing of the semiconductor device (col. 2, lines 7-14).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US Pat # 6,509,232 to Kim et al. (Kim) in view of US Pub # 2014/0349464 to Yang et al (Yang) and further in view of US pat # 7,723,755 to Lee et al. (Lee).
Regarding claim 8, Kim and Yang disclose all of the limitations of claim 2 from which this claim depends.
Kim and Yang fail to discloses wherein the plurality of word-lines comprise titanium nitride.
Lee discloses wherein the plurality of word-lines comprise titanium nitride.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to form the word lines of Kim using titanium nitride as taught by Lee because TiN is a well-known conductive gate material used in semiconductor devices due to its good conductivity, thermal stability, and compatibility with semiconductor fabrication processes (col. 1, lines 51-55).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 6821843 to Chen et al., US Pat # 6426256 to Chen., US Pub # 2021/0098606 to Bian., US Pat # 8207596 to Wang and US Pub # 2007/0015327 to Su.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896