DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1, 3, 5-7 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, Hee-Jin (Pub No. US 20140233249 A1) (hereinafter, Lee).
Re Claim 1, Lee teaches a chip on film package comprising:
a base film (Base film; 21; Fig 5; ¶[0036]);
output wiring (Output wire pattern; 24; Fig 5; ¶[0034]) disposed on the base film and extending along a first direction (Vertical direction; Fig 5);
an insulation layer (Solder resist; 25; Fig 6; ¶[0039]) overlapping at least a portion (Upper portions of 24; Fig 6) of the output wiring;
an output pad portion (Pad electrodes (not illustrated); ¶[0045]) defined as a region in which the output wiring is exposed (The pad electrodes connecting output wiring to display panel are requires to be connected to the exposed portion of output wiring; ¶[0045]);
a semiconductor chip (Semiconductor chip; 10; Figs 5/6; ¶[0035]) mounted on the base film and electrically connected (¶[0034]) to the output wiring; and
a protective layer (Protection films; 271/272; Fig 5; ¶[0060]) disposed between the semiconductor chip and the output pad portion with respect to the first direction, and spaced apart from the output pad portion. (See Figs 5/6 below)
Lee, Figs 5/6: Plan and side view of tape package and flat panel display device
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Re Claim 3, Lee teaches the chip on film package of claim 1, wherein the protective layer (Protection films; 271/272; Fig 5; ¶[0060]) has a width greater than or equal to a predetermined minimum width (Larger width than the solder resist in lengthwise direction; ¶[0014]) with respect to the first direction (Vertical direction; Fig 5).
Re Claim 5, Lee teaches the chip on film package of claim 1, wherein the protective layer (Protection films; 271/272; Fig 6; ¶[0060]) is positioned on the insulation layer (Solder resist; 25; Fig 6; ¶[0039]).
Re Claim 6, Lee teaches the chip on film package of claim 1, wherein the protective layer (Protection films; 271/272; Fig 6; ¶[0060]) is positioned on a first surface (Upper surface of 21) of the base film (Base film; 21; Fig 6; ¶[0036]).
Re Claim 7, Lee teaches a chip on film package comprising:
a base film (Base film; 21; Fig 5; ¶[0036]);
output wiring (Output wire pattern; 24; Fig 5; ¶[0034]) disposed on the base film and extending along a first direction (Vertical direction; Fig 5);
an insulation layer (Solder resist; 25; Fig 6; ¶[0039]) overlapping at least a portion (Upper portions of 24; Fig 6) of the output wiring;
an output pad portion (Pad electrodes (not illustrated); ¶[0045]) defined as a region in which the output wiring is exposed (The pad electrodes connecting output wiring to display panel are requires to be connected to the exposed portion of output wiring; ¶[0045]);
a semiconductor chip (Semiconductor chip; 10; Figs 5/6; ¶[0035]) mounted on the base film and electrically connected (¶[0034]) to the output wiring; and
a protective layer (Protection films; 271/272; Fig 5; ¶[0060]) disposed between the semiconductor chip and the output pad portion with respect to the first direction and having a width greater than or equal to a predetermined minimum width (Larger width than the solder resist in lengthwise direction; ¶[0014]).
Re Claim 10, Lee teaches the chip on film package of claim 7, wherein the protective layer (Protection films; 271/272; Fig 5; ¶[0060]) is spaced apart (Spaced vertically from lower exposed output wire pattern; Fig 5) from the output pad portion (Pad electrodes (not illustrated); ¶[0045]).
Re Claim 11, Lee teaches the chip on film package of claim 7, wherein the protective layer (Protection films; 271/272; Fig 6; ¶[0060]) is positioned on the insulation layer (Solder resist; 25; Fig 6; ¶[0039]).
Re Claim 12, Lee teaches the chip on film package of claim 7, wherein the protective layer (Protection films; 271/272; Fig 6; ¶[0060]) is positioned on a first surface (Upper surface of 21) of the base film (Base film; 21; Fig 6; ¶[0036]).
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 2, 4 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Hee-Jin (Pub No. US 20140233249 A1) (hereinafter, Lee) as applied to claims 1 and 7 above.
Re Claim 2, Lee does not teach the chip on film package of claim 1, wherein the protective layer is disposed spaced apart from the output pad portion by 10 um or more.
Lee fails to disclose the exact spacing of the protective layer and output pad portion as claimed.
Nevertheless, as depicted in Figure 5 such features (spacing of the protective layer and output pad portion) must possess particular dimension. The choice of the spacing of the protective layer and output pad portion, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Lee's spacing of the protective layer and output pad portion because this would be the best engineering design choice.
In addition, the selection of the particular ranges as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 4, Lee does not teach the chip on film package of claim 1, wherein the protective layer has a thickness greater than or equal to a predetermined minimum thickness.
Lee fails to disclose the exact thickness of the protective layer as claimed.
Nevertheless, as depicted in Figure 6 such features (thickness of the protective layer) must possess particular dimension. The choice of the thickness of the protective layer, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Lee's thickness of the protective layer because this would be the best engineering design choice.
In addition, the selection of the particular ranges as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 8, Lee does not teach the chip on film package of claim 7, wherein the width of the protective layer is greater than or equal to 1 mm with respect to the first direction.
Lee fails to disclose the exact width of the protective layer as claimed.
Nevertheless, as depicted in Figure 5 such features (width of the protective layer) must possess particular dimension. The choice of the width of the protective layer, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Lee's width of the protective layer because this would be the best engineering design choice.
In addition, the selection of the particular ranges as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 9, Lee does not teach the chip on film package of claim 7, wherein the protective layer has a thickness greater than or equal to a predetermined minimum thickness.
Lee fails to disclose the exact thickness of the protective layer as claimed.
Nevertheless, as depicted in Figure 6 such features (thickness of the protective layer) must possess particular dimension. The choice of the thickness of the protective layer, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Lee's thickness of the protective layer because this would be the best engineering design choice.
In addition, the selection of the particular ranges as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
9. Claims 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Hee-Jin (Pub No. US 20140233249 A1) (hereinafter, Lee), and further in view of Ha, Jeong-Kyu (Pub No. US 20160218065 A1) (hereinafter, Ha).
Re Claim 13, Lee teaches a display device comprising:
a chip on film package (Chip-on-film package above display panel 30; Fig 6); and
a panel mechanism (Second substrate; 32; Fig 6; ¶[0046]) positioned between the display panel and the chip on film package,
wherein the chip on film package comprises:
a base film (Base film; 21; Fig 5; ¶[0036]);
output wiring (Output wire pattern; 24; Fig 5; ¶[0034]) disposed on the base film and extending along a first direction (Vertical direction; Fig 5);
an insulation layer (Solder resist; 25; Fig 6; ¶[0039]) overlapping at least a portion (Upper portions of 24; Fig 6) of the output wiring;
an output pad portion (Pad electrodes (not illustrated); ¶[0045]) defined as a region in which the output wiring is exposed (The pad electrodes connecting output wiring to display panel are requires to be connected to the exposed portion of output wiring; ¶[0045]);
a semiconductor chip (Semiconductor chip; 10; Figs 5/6; ¶[0035]) mounted on the base film and electrically connected (¶[0034]) to the output wiring; and
a protective layer (Protection films; 271/272; Fig 5; ¶[0060]) disposed between the semiconductor chip and the output pad portion with respect to the first direction and having a width greater than or equal to a predetermined minimum width (Larger width than the solder resist in lengthwise direction; ¶[0014]).
However, Lee does not teach a display panel comprising a plurality of data lines and a plurality of gate lines.
In the same field of endeavor, Ha teaches a display panel (Display panel; 220; Fig 5B; ¶[0087]) comprising a plurality of data lines (Data lines in panel substrate 210; Fig 5B; ¶[0087]) and a plurality of gate lines (Gate lines in panel substrate 210; Fig 5B; ¶[0087]).
Ha, Figs 5A/5B: Plan and side view of package module according to an embodiment
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the display panel comprising a plurality of data lines and a plurality of gate lines, as taught by Ha, with the chip on film package, as taught by Lee. One would have been motivated to do this with a reasonable expectation of success because the electrical signals generated from the semiconductor chip may be provided to gate lines and/or data lines of the panel substrate through the output interconnection lines, so the display panel may be driven, as suggested by Ha (¶[0087]).
Re Claim 14, Lee teaches the display device of claim 13, wherein the wherein the protective layer (Protection films; 271/272; Fig 5; ¶[0060]) is spaced apart (Spaced vertically from lower exposed output wire pattern; Fig 5) from the output pad portion (Pad electrodes (not illustrated); ¶[0045]).
Re Claim 15, Lee teaches the display device of claim 13, wherein the protective layer (Protection films; 271/272; Fig 5; ¶[0060]) has a width greater than or equal to a predetermined minimum width (Larger width than the solder resist in lengthwise direction; ¶[0014]) with respect to the first direction (Vertical direction; Fig 5).
Re Claim 16, Lee in view of Ha does not teach the display device of claim 13, wherein the thickness of the protective layer is greater than or equal to 15 um.
Lee fails to disclose the exact thickness of the protective layer as claimed.
Nevertheless, as depicted in Figure 6 such features (thickness of the protective layer) must possess particular dimension. The choice of the thickness of the protective layer, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Lee's thickness of the protective layer because this would be the best engineering design choice.
In addition, the selection of the particular ranges as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 17, Lee teaches the display device in claim 13, wherein the protective layer (Protection films; 271/272; Fig 6; ¶[0060]) is positioned on a first surface (Upper surface of 21) of the base film (Base film; 21; Fig 6; ¶[0036]).
Re Claim 18, Lee teaches the display device of claim 13, wherein the protective layer (Protection films; 271/272; Fig 6; ¶[0060]) is positioned on the insulation layer (Solder resist; 25; Fig 6; ¶[0039]).
Re Claim 19, Lee teaches the display device of claim 13, wherein the protective layer (Protection films; 271/272; Fig 6; ¶[0060]) is positioned on a first surface (Upper surface of 21; Fig 6) of the base film (Base film; 21; Fig 6; ¶[0036]). having the output wiring and the insulation layer (Solder resist; 25; Fig 6; ¶[0039]) formed thereon (Output wiring 24 and solder resist 25 formed on base film 21; Fig 6).
Re Claim 20, Lee teaches the display device of claim 13, wherein the protective layer (Protection films; 271/272; Fig 6; ¶[0060]) has a width (Horizontal width; Fig 5) less than or equal to the insulation layer (Solder resist; 25; Fig 5; ¶[0039]) with respect to the second direction (Horizontal direction in Fig 5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Park, Ji-Yong et al. (Pub No. US20220013476A1) discloses a semiconductor package including a base film that has a first surface and a second surface opposite to the first surface, a plurality of input/output lines on the first surface of the base film, a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines and including a central portion and end portions on opposite sides of the central portion, and a heat radiation pattern on the second surface of the base film The heat radiation pattern corresponds to the semiconductor chip and has a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip.
[2] Chung, Ye-Chung et al. (Pub No. US20080128902A1) discloses A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817