DETAILED ACTION
This action is responsive to the application filed September 5, 2023. Claims 1-20 are pending. Claims 1, 9, and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amendment to the title of the invention is acknowledged and accepted. The objection to the title has been withdrawn.
Response to Amendment
The reply filed on September 5, 2025, is not fully responsive to the prior Office action because of the following omission(s) or matter(s): Applicant is reminded to show support for amended claims as per MPEP 2163(II)(A) and see 37 CFR 1.111. Since, upon review of the drawings and specification, support was found in Fig. 6 and para. 18, and because the above-mentioned reply appears to be bona fide, discretion is exercised to treat the amendment as an adequate reply rather than requiring the reply to be completed to avoid abandonment as per MPEP 713.03.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 6-8, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aritome (US 20150003150 – of Record).
Regarding independent claim 1, Aritome discloses a memory device comprising:
a plurality of strings connected between a bit line and a source line (Fig. 3 where it illustrates memory cells in strings connected between bit lines BL and source lines SL. See also para 10; "a semiconductor device may include a plurality of memory blocks comprising a plurality of cell strings");
and a peripheral circuit configured to simultaneously perform an erase operation on the plurality of strings (para. 13; "the method comprising erasing memory cells included in a selected memory block, connected to the plurality of source lines and the plurality of bit lines, by applying an erase voltage to the plurality of bit lines and the plurality of source lines connected to the selected memory block". As noted above, each memory block comprises a plurality of cell strings),
perform an erase verify operation on the plurality of strings (para. 13; "verifying that the memory cells are erased". It is noted that the Aritome's erase verify operation is applied to the same plurality of strings as the erase operation above),
determine a first string and a second string among the plurality of strings based on a result of the erase verify operation (para. 88; "the erase verification operation may be performed in the cell string group CSG units". See also para. 89; "The cell strings that passed the erase verification operation may be erase inhibition cell strings In. ST", "The cell strings ST that did not pass the erase verification operation may be defined as the selected cell strings Sel. ST". Therefore, Sel. ST is the first string, and In. ST is the second string),
re-perform an erase operation on the first string by applying an erase voltage to at least one of the bit line and the source line (Fig. 6 which illustrates that strings Sel. ST which did not pass erase verify get another erase loop iteration. See also para. 90; "While the erase operation is carried out, the memory cells included in the selected cell strings Sel. ST may be erased by applying the erase voltage to selected bit lines Sel. BL and selected source lines Sel. SL"),
and control the second string to be prohibited from being erased while the erase voltage is applied to the at least one of the bit line and the source line (para. 13; "applying an erase inhibition voltage to bit lines, of the plurality of bit lines, connected to the cell strings that have been erased, and to source lines, of the plurality of source lines, connected to the cell strings that have been erased").
Regarding claim 6, Aritome discloses the limitations of claim 1.
As applied, Aritome further discloses wherein the peripheral circuit is configured to
perform the erase verify operation on each of string sets in which the plurality of strings are grouped (para. 13; "verifying that the memory cells are erased”. See also Fig. 5 & 6 where it illustrates the erase verify operation over a plurality of strings. It is noted that the terms "first string" and "second string" are interpreted to mean strings of memory cells which have either passed or not passed the erase verify operation).
Regarding claim 7, Aritome discloses the limitations of claim 6.
As applied, Aritome further discloses wherein the peripheral circuit is configured to determine, as the first string, a string in a string set, on which the result of the erase verify operation is erase-fail and determine, as the second string, a string in a string set, on which the result of the erase verify operation is erase-pass. (para. 93; "When all of the memory cells included in the selected memory block Sel. BLK by repeating the erase operation as described above pass the erase verification operation, the erase operation is completed").
Regarding claim 8, Aritome discloses the limitations of claim 1.
As applied, Aritome further discloses wherein each of the plurality of strings includes one or more drain select transistors (Fig. 3:DST),
one or more source select transistors (Fig. 3:SST), and
a plurality of memory cells connected between the one or more drain select transistors and the one or more source select transistors (Fig. 3:MC),
wherein the one or more drain select transistors, the plurality of memory cells, and the one or more source select transistors are connected in series between the bit line and the source line (Fig. 3:BLn & SLn),
and wherein each of the one or more drain select transistors and the one or more source select transistors is configured to be turned on in response to corresponding select line. (Fig. 3:DSL1 & SSL1 for example).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 9, 13-15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 20150003150 – of Record) in view of Lee et al. (US 20200211650; “Lee2”).
Regarding independent claim 9, Aritome discloses a memory device comprising:
a plurality of strings connected between a bit line and a source line (Fig. 3 where it illustrates memory cells in strings connected between bit lines BL and source lines SL. See also para 10; " a semiconductor device may include a plurality of memory blocks comprising a plurality of cell strings");
and a peripheral circuit configured to simultaneously perform an erase operation on the plurality of strings (para. 13; "the method comprising erasing memory cells included in a selected memory block, connected to the plurality of source lines and the plurality of bit lines, by applying an erase voltage to the plurality of bit lines and the plurality of source lines connected to the selected memory block". As noted above, each memory block comprises a plurality of cell strings),
perform an erase verify operation on the plurality of strings (para. 13; "verifying that the memory cells are erased". It is noted that the Aritome's erase verify operation is applied to the same plurality of strings as the erase operation above),
determine a first string and a second string among the plurality of strings based on a result of the erase verify operation (para. 88; "the erase verification operation may be performed in the cell string group CSG units". See also para. 89; "The cell strings that passed the erase verification operation may be erase inhibition cell strings In. ST", "The cell strings ST that did not pass the erase verification operation may be defined as the selected cell strings Sel. ST". Therefore, Sel. ST is the first string, and In. ST is the second string),
Aritome is silent regarding floating select lines during the erase operation.
However, Lee2 teaches apply, during a first section in which the peripheral circuit applies a first erase voltage to at least one of the bit line and the source line, an erase select voltage to a plurality of select lines connected to the first string while a plurality of select lines connected to the second string are floated (Fig. 9 where it illustrates a first erase voltage Vera1 applied to the source line at the first section, and the erase select voltage (0V) applied to a first plurality of select lines (SSL4-SSL7), and floating a plurality of select lines (SSL1-SSL3)),
and float, during a second section in which the peripheral circuit applies a second erase voltage to at least one of the bit line and the source line, the plurality of select lines connected to the first string and the second string (Fig. 9 where it illustrates a second erase voltage Vera2 applied to the source line at the second section, and floating all of the select lines (SSL1-SSL3)).
Aritome and Lee2 are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology with the teachings of Lee2’s floating the select lines during the erase operation. Doing so would help ensure the erase operation does not over erase some memory cells.
Regarding claim 13, Aritome and Lee2 combined disclose the limitations of claim 9.
As applied, Aritome further discloses wherein the peripheral circuit is configured to
perform the erase verify operation on each of string sets in which the plurality of strings are grouped (para. 13; "verifying that the memory cells are erased. It is noted that the term string groups are interpreted to mean strings of memory cells which have either passed or not passed the erase verify operation).
Regarding claim 14, Aritome and Lee2 combined disclose the limitations of claim 13.
As applied, Aritome further discloses wherein the peripheral circuit is configured to determine, as the first string, a string in a string set, on which the result of the erase verify operation is erase-fail and configured to determine, as the second string, a string in a string set, on which the result of the erase verify operation is erase-pass (para. 93; "When all of the memory cells included in the selected memory block Sel. BLK by repeating the erase operation as described above pass the erase verification operation, the erase operation is completed").
Regarding independent claim 15, Aritome discloses a memory device comprising:
a plurality of strings connected between a bit line and a source line (Fig. 3 where it illustrates memory cells in strings connected between bit lines BL and source lines SL. See also para 10; " a semiconductor device may include a plurality of memory blocks comprising a plurality of cell strings");
and a peripheral circuit configured to simultaneously perform an erase operation on the plurality of strings by applying an erase voltage to at least one of the bit line and the source line (para. 13; "the method comprising erasing memory cells included in a selected memory block, connected to the plurality of source lines and the plurality of bit lines, by applying an erase voltage to the plurality of bit lines and the plurality of source lines connected to the selected memory block". As noted above, each memory block comprises a plurality of cell strings),
perform an erase verify operation on the plurality of strings (para. 13; "verifying that the memory cells are erased". It is noted that the Aritome's erase verify operation is applied to the same plurality of strings as the erase operation above),
determine a non-target string among the plurality of strings based on a result of the erase verify operation (para. 88; "the erase verification operation may be performed in the cell string group CSG units". See also para. 89; "The cell strings that passed the erase verification operation may be erase inhibition cell strings In. ST", "The cell strings ST that did not pass the erase verification operation may be defined as the selected cell strings Sel. ST". Therefore, Sel. ST is the first string, and In. ST is the second string),
Aritome is silent regarding floating select lines during the erase operation.
However, Lee2 teaches and float, while the erase voltage is reapplied to the at least one of the bit line and the source line, a plurality of select lines connected to the non-target string to prohibit a plurality of memory cells of the non-target string from being erased (Fig. 9 where it illustrates a plurality of select strings floating while an erase voltage is applied to the source line. It is noted that Lee's floating select lines connect to a plurality of strings, some of which will have passed the erase verify operation (i.e.: non-target) and therefore will be inhibited from further erase).
Aritome and Lee2 are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology with the teachings of Lee2’s floating the select lines during the erase operation. Doing so would help ensure the erase operation does not over erase some memory cells.
Regarding claim 19, Aritome and Lee2 discloses the limitations of claim 15.
As applied, Aritome further discloses wherein the peripheral circuit is configured to
perform the erase verify operation on each of string sets in which a plurality of strings are grouped (para. 13; "verifying that the memory cells are erased").
Regarding claim 20, Aritome and Lee2 discloses the limitations of claim 19.
As applied, Aritome further discloses wherein the peripheral circuit is configured to determine, as the non-target string, a string in a string set, on which the result of the erase verify operation is erase-pass (para. 93; "When all of the memory cells included in the selected memory block Sel. BLK by repeating the erase operation as described above pass the erase verification operation, the erase operation is completed").
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 20150003150 – of Record) in view of Oh et al. (US 20120257455; “Oh1” – of Record).
Regarding claim 2, Aritome discloses the limitations of claim 1.
Aritome is silent with respect to floating the select lines during the erase operation.
However, Oh1 teaches wherein the peripheral circuit is configured to float a plurality of select lines connected to the second string during an entire duration, in which the peripheral circuit applies the erase voltage (Fig. 20 where it illustrates the unselected select lines (second string) set to float. See also para.177; "FIG. 20 is a table illustrating voltages supplied to a memory block at an erase operation", "String selection lines SSL1 and SSL2 may be floated").
Aritome and Oh1 are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology with the teachings of Oh1’s floating the select lines during the erase operation to cause gate induced drain leakage current. Doing so would drive hot holes into the channel improving the erase threshold voltage.
Regarding claim 5, Aritome discloses the limitations of claim 1.
Aritome is silent with respect to applying an erase select voltage to the word lines.
However, Oh1 teaches wherein the peripheral circuit is configured to apply an erase select voltage lower than the erase voltage to a plurality of word lines connected to the plurality of strings during an entire duration, in which the peripheral circuit applies the erase voltage (Fig. 20 where it illustrates the word lines (WL) set to VSS during the erase operation. See also para. 177; "A ground voltage VSS may be applied to word lines WL1-WL6". It is noted that the erase selected voltage is defined in the instant application as ground (para. 37). Fig. 23 indicates the erase voltage (Vers) is higher than ground).
Aritome and Oh1 are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology with the teachings of Oh1’s floating the select lines during the erase operation to cause gate induced drain leakage current. Doing so would drive hot holes into the channel improving the erase threshold voltage.
Claims 10, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 20150003150 – of Record) in view of Lee et al. (US 20200211650; “Lee2”) and further in view of Oh et al. (US 20120257455; “Oh1” – of Record).
Regarding claim 10, Aritome and Lee2 combined disclose the limitations of claim 9.
Aritome and Lee2 are silent with respect to the word line voltage during both erase phases.
However, Oh1 teaches discloses wherein the peripheral circuit is configured to apply the erase select voltage to a plurality of word lines connected to the plurality of strings during the first section and the second section (Fig. 20 where it illustrates the word lines (WL) set to VSS during the erase operation. See also para. 177; "A ground voltage VSS may be applied to word lines WL1-WL6". It is noted that the erase selected voltage is defined in the instant application as ground (para. 37). Fig. 23 indicates the erase voltage (Vers) is higher than ground. It is further noted that the terms "first section" and "second section" are merely defined as being "subsequent" (Spec. para. 49) as illustrated by LE1, and LE2 in Oh's Fig. 23 for example).
Aritome, Lee2 and Oh1 are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology with the teachings of Lee2’s floating the select lines with Oh1’s teachings of grounding the select word lines during an erase operation. Doing so would provide a complete erase of memory cells without over erasing.
Regarding claim 12, Aritome and Lee2 combined disclose the limitations of claim 9.
Aritome and Lee2 are silent with respect to the magnitude differences between the erase voltages.
However, Oh1 teaches wherein the erase select voltage is lower than the first erase voltage (Fig. 20 where it illustrates the word lines (WL) set to VSS during the erase operation. See also para. 177; "A ground voltage VSS may be applied to word lines WL1-WL6". It is noted that the erase selected voltage is defined in the instant application as ground (para. 37). Fig. 23 indicates the erase voltage (Vers) is higher than ground), and
wherein the second erase voltage is higher than the first erase voltage (Fig. 23 where it illustrates the second section (LE2) with a second erase voltage (higher by delta-VE)).
Aritome, Lee2 and Oh1 are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology with the teachings of Lee2’s floating the select lines with Oh’s teachings of the magnitude differences between select and erase voltages during an erase operation. Doing so would provide a complete erase of memory cells without over erasing.
Regarding claim 18, Aritome and Lee2 discloses the limitations of claim 15.
Aritome and Lee 2 are silent with respect to an erase select voltage lower than the erase voltage.
However, Oh1 teaches wherein the peripheral circuit is configured to apply an erase select voltage lower than the erase voltage to a plurality of word lines connected to the plurality of strings during the applying of the erase voltage (Fig. 20 where it illustrates the word lines (WL) set to VSS during the erase operation. See also para. 177; "A ground voltage VSS may be applied to word lines WL1-WL6". It is noted that the erase selected voltage is defined in the instant application as ground (para. 37). Fig. 23 indicates the erase voltage (Vers) is higher than ground.).
Aritome, Lee2 and Oh1 are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology with the teachings of Lee’s floating of the select lines, with the teachings of Oh1’s lower select erase voltage during the erase operation to lower the threshold voltage of the cells to be erased. Doing so would improve the margin of the erase threshold voltage.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 20150003150 – of Record) in view of Han et al. (US 20110199825; “Han” – of Record).
Regarding claim 3, Aritome discloses the limitations of claim 1.
Aritome is silent with respect to specific “sections” of time within the erase operation.
However, Han teaches wherein the peripheral circuit is configured to apply, during a first section in which the peripheral circuit applies a first erase voltage as the erase voltage (Fig. 45. See also para. 425; ""FIG. 45 is a table illustrating example embodiments of voltage conditions during an erase operation". See also para. 427; "At a first timing t1, a pre voltage Vpre is applied to a substrate 111". It is noted that Vpre is analogous to the first erase voltage (para. 425) and the substrate is the source line (para. 41)),
an erase select voltage lower than the first erase voltage to a plurality of select lines connected to the first string (para. 428; "At a first timing t1, a ground voltage Vss is applied to the ground selection line GSL". It is noted that Fig. 7 illustrates a plurality of select lines. Further, the term "erase select voltage" is defined in the instant application as ground (para. 37)) and
configured to float the plurality of select lines during a second section (para. 433; "At a second timing t2, the ground selection line GSL floats") in which the peripheral circuit applies a second erase voltage as the erase voltage, the second section being subsequent to the first section (para. 432; "At a second timing t2, a second erase voltage Vers2 is applied to the substrate 111").
Aritome and Han are from the same field of endeavor as applicant’s invention directed to erase techniques for non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology with the teachings of Han’s multi-phase erase operation to utilize gate induced drain leakage to the lower the threshold voltage of the cells to be erased. Doing so would reduce the size of the threshold voltage distribution on erased cells, improving memory reliability.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 20150003150 – of Record) in view of Han et al. (US 20110199825; “Han” – of Record) and further in view of Lee et al. (US 20030117856; “Lee1” of Record) and further in view of Oh (US 20200321066; “Oh2”).
Regarding claim 4, Aritome and Han combined disclose the limitations of claim 3.
Aritome and Han are silent with respect to a third section, after the erase operation.
However, Lee1 teaches the peripheral circuit is configured to stop, during a third section subsequent to the second section, the applying of the second erase voltage while the bit line (para 127; "In time segment 3, bit lines BLe, BLo are grounded for discharge. In time segment 4, a Verify Read operation takes place". It is noted that the erase voltage would necessarily be stopped during the bit line discharge prior to the verify operation),
Aritome, Han, and Lee1 are silent with respect to explicitly discharging the source line, and select lines after the erase operation.
However, Oh2 teaches the source line and a plurality of select lines connected to the plurality of strings are discharged (Fig. 7 where it illustrates the source line (SL) and select line (SSL) connected to the strings. It is noted that Fig. 5 illustrates the plurality of select lines connected to the strings).
Aritome, Han, Lee1 and Oh2 are from the same field of endeavor as applicant’s invention directed to methods of operating a non-volatile memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s and Han’s multi-phase erase operation with Lee1’s bit line discharge and Oh2’s source and select line discharging after the erase operation to optimize the channel voltage at the end of the erase operation. Doing so would reduce the time to erase the memory cells and therefore speed up the device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 20150003150 – of Record) in view of Lee et al. (US 20200211650; “Lee2”) and further in view of Lee et al. (US 20030117856; “Lee1” – of Record) and further in view of Oh (US 20200321066; “Oh2”).
Regarding claim 11, Aritome and Lee2 combined disclose the limitations of claim 9.
Aritome and Lee2 combined are silent with respect to a third section after the erase operation.
However, Lee1 teaches wherein the peripheral circuit is configured to stop, during a third section subsequent to the second section, the applying of the second erase voltage while the bit line (para 127; “In time segment 3, bit lines BLe, BLo are grounded for discharge. In time segment 4, a Verify Read operation takes place". It is noted that the erase voltage would necessarily be stopped during the bit line discharge prior to the verify operation.),
Aritome, Lee2, and Lee1 are silent with respect to explicitly discharging the source line, and select lines after the erase operation.
However, Oh2 teaches the source line and the plurality of select lines connected to the strings are discharged (Fig. 7 where it illustrates the source line (SL) and select line (SSL) connected to the strings. It is noted that Fig. 5 illustrates the plurality of select lines connected to the strings).
Aritome, Lee2, Lee1 and Oh2 are from the same field of endeavor as applicant’s invention directed to methods of operating a non-volatile memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s and Lee2’s multi-phase erase operation with Lee1’s bit line discharge and Oh2’s source and select line discharging after the erase operation to optimize the channel voltage at the end of the erase operation. Doing so would reduce the time to erase the memory cells and therefore speed up the device.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 20150003150 – of Record) in view of Lee et al. (US 20200211650; “Lee2”) and further in view of Han et al. (US 20110199825; “Han” – of Record)
Regarding claim 16, Aritome and Lee2 combined disclose the limitations of claim 15.
Aritome and Lee2 combined are silent with respect to specific “sections” of time within the erase operation.
However, Han teaches wherein the peripheral circuit is configured to apply, during a first section in which the peripheral circuit applies a first erase voltage as the erase voltage (Fig. 45. See also para. 425; "FIG. 45 is a table illustrating example embodiments of voltage conditions during an erase operation". See also para. 427; "At a first timing t1, a pre voltage Vpre is applied to a substrate 111". It is noted that Vpre is analogous to the first erase voltage (para. 425) and the substrate is the source line (para. 41)),
an erase select voltage lower than the first erase voltage to a plurality of select lines connected to a target string among the plurality of strings (para. 428; "At a first timing t1, a ground voltage Vss is applied to the ground selection line GSL". It is noted that the term "erase select voltage" is defined in the instant application as ground (para. 37). Also see para 28; “In example embodiments, each of the plurality of memory blocks includes at least two string select transistors and at least two ground select transistors”)
and configured to float, during a second section in which the peripheral circuit applies a second erase voltage as the erase voltage, the plurality of select lines connected to the target string (para. 433; "At a second timing t2, the ground selection line GSL floats". See also Fig. 8 where it illustrates the select string (GSL) connected to the memory strings), the second section being subsequent to the first section (para. 432; "At a second timing t2, a second erase voltage Vers2 is applied to the substrate 111").
Aritome, Lee2 and Han are from the same field of endeavor as applicant’s invention directed to operation of non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s array topology combined with Lee2’s floating select line with the teachings of Han’s multi-phase erase operation to utilize gate induced drain leakage to the lower the threshold voltage of the cells to be erased. Doing so would reduce the size of the threshold voltage distribution on erased cells, improving memory reliability.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Aritome (US 20150003150 – of Record) in view of Lee et al. (US 20200211650; “Lee2”) and further in view of Han et al. (US 20110199825; “Han” – of Record) and further in view of Lee et al. (US 20030117856; “Lee1” – of Record) and further in view of Oh (US 20200321066; “Oh2”).
Regarding claim 17, Aritome, Lee2 and Han combined disclose the limitations of claim 16.
Aritome, Lee2 and Han combined are silent with respect to a third section of the erase operation.
However, Lee1 teaches wherein the peripheral circuit is configured to stop, during a third section subsequent to the second section, the applying of the second erase voltage while the bit line (para 127; "In time segments 1 and 2, an erase execution command is received. In time segment 3, bit lines BLe, BLo are grounded for discharge. In time segment 4, a Verify Read operation takes place". It is noted that the erase voltage would necessarily be stopped during the bit line discharge prior to the verify operation),
Aritome, Lee2, Han and Lee1 are silent with respect to explicitly discharging the source line and select lines after the erase operation.
However, Oh2 teaches the source line and the plurality of select lines connected to the strings are discharged (Fig. 7 where it illustrates the source line (SL) and select line (SSL) connected to the strings. It is noted that Fig. 5 illustrates the plurality of select lines connected to the strings).
Aritome, Lee2, Han, Lee1 and Oh2 are from the same field of endeavor as applicant’s invention directed to methods of operating a non-volatile memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Aritome’s, Lee2’s and Han’s multi-phase erase operation with Lee1’s bit line discharge and Oh2’s source and select line discharging after the erase operation to optimize the channel voltage at the end of the erase operation. Doing so would reduce the time to erase the memory cells and therefore speed up the device.
Response to Arguments
Applicant's arguments filed September 4, 2025, with respect to independent claims 1, 9, and 15, have been fully considered but because different facts and newly cited portions from the previously applied references in combination with the new references applied, are either unpersuasive or moot because of the new ground of rejection.
Applicant argues that the anticipation rejection of claim 1 is improper because Aritome performs the erase operation on different blocks instead of different strings within the same block and therefore the erase operation is not simultaneously performed as presently claimed.
In the current rejection above, Aritome’s erase is applied to a plurality of strings within one block simultaneously as well as determining two groupings of memory cells being either fully erased or not as presently claimed.
Additionally, for independent claims 9 and 15, new reference Lee2 is cited which reads on the amended limitations regarding the various voltages applied to other signals of interest during the erase operation claimed.
For at least these reasons, the rejections of the independent claims of the instant application are deemed proper and maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825