DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (Wang, US 2019/0157209 A1).
Regarding claim 1, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), comprising: a circuit substrate (circuit substrate CB in FIG. 22) having a first surface (top surface of CB) and a second surface ( bottom surface of CB) disposed oppositely (see FIG 22), wherein the circuit substrate (CB) comprises an opening ( opening of 150 via) that penetrates through the circuit substrate (CB) in a direction from the first surface (top surface of CB) towards the second surface (bottom surface of CB); a first chip (chip 120); a second chip (chip 110), wherein the second chip (chip 110) is fixed on the first surface of the circuit substrate (CB), and the first chip (chip 120) is fixed on a surface of the second chip away from the circuit substrate (CB); a first conductive assembly connecting the first chip (chip 120) and the circuit substrate (CB); and a second conductive assembly (see FIG. 22), wherein a part of the second conductive assembly penetrates through the opening ( via 150), and the second conductive assembly connects the second chip and the circuit substrate (CB).
Regarding claim 2, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the first chip (chip 120) has a first active surface and a first back surface disposed oppositely (see FIG. 22), the first back surface of the first chip (chip[ 120) is fixed on the second chip (Chip 110), and a first pad is disposed on the first active surface (see FIG. 22).
Regarding claim 3, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the first conductive assembly comprises: first wires (wire WR1/WR2), one end of each of the first wires being fixed on the first pad of the first active surface, and other ends of each of the first wires being fixed on the first surface of the circuit substrate (CB).
Regarding claim 4, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the first conductive assembly further comprises: conductive bridging blocks ( interface between chip and redistribution layer) fixed on at least one of the first chip (chip 120) and the second chip (chip 1220); and the first wires comprise first wire (WR1/WR2) segments and second wire segments, two opposite ends of the first wire segments being fixed on the conductive bridging blocks and the first pad of the first active surface respectively (see Fig. 22), and two opposite ends of the second wire segments being fixed on the conductive bridging blocks and the first surface of the circuit substrate respectively (see FIG. 22).
Regarding claim 5, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the conductive bridging blocks are fixed on the first active surface of the first chip (active surface of chip 120), and are disposed as being spaced apart from the first pad (pad of chip 120).
Regarding claim 6, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the conductive bridging blocks are fixed on the surface of the second chip (chip 110) far away from the circuit substrate (substrate CB), and are disposed as being spaced apart from the first chip (chip 120).
Regarding claim 7, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the first conductive assembly further comprises: carriers, wherein the carriers are fixed on at least one of the first chip and the second chip, and a plurality of the conductive bridging blocks are located on the carriers (c1 in [0028]).
Regarding claim 8, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the carriers include at least one of a semiconductor substrate ( chip 120/110 comprise semiconductor substrate) and a circuit board (CB).
Regarding claim 9, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the circuit substrate further comprises: pins (see connection pin on top of chip 110) located on the first surface of the circuit substrate (CB), disposed as being spaced apart from the second chip, and connected with the circuit substrate, wherein other ends of the first wires are fixed on the pins (see FIG. 22).
Regarding claim 10, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the second chip (chip 110) has a second active surface (top surface of chip 120) and a second back surface (back surface 120) disposed oppositely, the second active surface of the second chip is fixed on the first surface of the circuit substrate (CB), and a plurality of second pads (connection pad of chip 120) are disposed on the second active surface and are exposed in the opening (interface of 150 and pad); the second conductive assembly comprises second wires that penetrate through the opening, and two opposite ends of the second wires are fixed on the second pads and the second surface of the circuit substrate (CB) respectively.
Regarding claim 11, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the plurality of second pads (pad of chip 120) are located between two opposite edges of the second chip (Chip 120).
Regarding claim 12, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), further comprising: a first adhesion layer (DA1) that is disposed between the first chip (chip 120) and the second chip (chip 110), and adheres the first chip and the second chip (see FIG. 22).
Regarding claim 13, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), further comprising: a second adhesion layer (DA2) that is disposed between the second chip (chip 110) and the circuit substrate (CB), and adheres the second chip and the circuit substrate (CB).
Regarding claim 14, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), wherein the circuit substrate (CB) comprises a plurality of third pads (pads of CB) located on the second surface; and the chip package device further comprises: a ball grid array (ball grid 200) comprising a plurality of solder balls located on the plurality of third pads (see FIG. 22).
Regarding claim 15, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), further comprising: a package layer (130) at least partially covering the first conductive assembly, the first chip (120), the second chip (110) and the circuit substrate (CB).
Regarding claim 16, Wang shows a chip package device (package chip 30 in FIG. 22 and [0071]), a chip package device comprising: a circuit substrate (CB) having a first surface and a second surface disposed oppositely, wherein the circuit substrate comprises an opening (VIA opening150) that penetrates through the circuit substrate (CB) in a direction from the first surface towards the second surface; a first chip (chip 110/120); a second chip (110/120), wherein the second chip is fixed on the first surface of the circuit substrate (CB), and the first chip is fixed on a surface of the second chip far away from the circuit substrate (CB); a first conductive assembly (interconnection conductive layer in 180) connecting the first chip and the circuit substrate (CB); and a second conductive assembly, wherein a part of the second conductive assembly penetrates through the opening (VIA opening 150), and the second conductive assembly connects the second chip and the circuit substrate (CB).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893