DETAILED ACTION
Request for Continued Examination
The request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 7/6/26 is accepted.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/6/26 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-12 and 19-20 are rejected under 35 U.S.C. 103 as being obvious over Chu (US 2023/0326854).
As to claim 1, Chu teaches an interconnection structure (see annotated fig. 2B below), comprising:
a substrate (obvious if not inherent, this device is on a PCB or motherboard at a minimum, which would be a substrate);
a first dielectric layer (100) disposed over the substrate ([0025] – [0027]);
a first metal trench (see below), disposed in the first dielectric layer, comprising:
a line portion (LP) extending along a first direction (D1), and
a protruding portion (PP) extending from the line portion along a second direction (D2) perpendicular to the first direction (D1);
a second dielectric layer (100) disposed over the first dielectric layer (100, ([0025] – [0027]), see explanation below);
a metal plate (see fig. below) disposed in the second dielectric layer (100), wherein the metal plate overlaps the protruding portion (PP) of the first metal trench, and wherein the metal plate is non-overlapping with the line portion (LP) of the first metal trench;
a connection via (see below) disposed in the second dielectric layer (100), wherein the connection via interconnects the metal plate and the first metal trench;
a third dielectric layer (200) disposed over the second dielectric layer; and
a hyper via (421 and/or 422) extending vertically through the third dielectric layer (200) and in contact with a top surface of the metal plate ([0028]).
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Chu does not explicitly teach dielectric layer 100 is comprised of multiple layers. However, Chu teaches dielectric layer 100 is a backside distribution network ([0025]). That is, it is a backside metallization/interconnection layer. Interconnection layers are known to have multiple lines and vias formed in a damascene manner, which means layer 100 would be comprised of multiple dielectric layers.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed that layer 100 would be comprised of multiple dielectric layers so as to fabricate multiple interconnects.
Since the metal plate, the connection via, and the metal trench are at different levels, they would also be in different layers.
As to claim 2, Chu further teaches the metal plate comprises an overlapping portion that overlaps the first metal trench in a vertical direction perpendicular to a surface of the substrate, and wherein the connection via extends from the overlapping portion of the metal plate to the first metal trench (see below).
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As to claim 3, Chu further teaches the connection via extends from the overlapping portion of the metal plate to the protruding portion (PP) of the first metal trench, and wherein the connection via is non-overlapping with the line portion (LP) of the first metal trench (see fig. above).
As to claim 4, Chu further teaches the metal plate comprises a center deviated from the first metal trench in the vertical direction (see fig. above).
As to claim 5, Chu further teaches the hyper via completely stands on the metal plate, the hyper via overlaps the protruding portion (PP) of the first metal trench (there is a slight overlapping), and the hyper via is non-overlapping with the line portion (LP) of the first metal trench (see fig. above).
As to claim 6, the ranges claimed are not taught but it is obvious that the plate is wider and longer than the width of the hyper via so that it will properly contact the metal plate. If that leads to the ranges claimed, then that is the result of ordinary skill in the art and not innovation.
As to claim 7, Chu further teaches a second metal trench disposed in the first dielectric layer (100), wherein the second metal trench is adjacent to the first metal trench, and wherein a bottom of the hyper via is non-overlapping with the second metal trench (see fig. above).
As to claims 9-12, Chu does not explicitly teach the dimensions and parameters claimed. However, determining the optimal dimensions for the hyper via would have been obvious so as to fabricate a device that meets design specification. Furthermore, the Applicant has not shown that these dimensions are novel and would NOT have been found through routine experimentation. Therefore, the dimensions claimed are not patentable over the prior art, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
As to claim 19, Chu teaches an interconnection structure (see annotated fig. 2B below), comprising:
a substrate (obvious if not inherent, this device is on a PCB or motherboard at a minimum, which would be a substrate);
a plurality of dielectric layers (100, 200, 300) that are stacked over the substrate ([0025] – [0027]);
a hyper via (421 and/or 422) that penetrates at least one of the dielectric layers (100 and 200, [0028]);
a metal plate disposed in one of the dielectric layers and in contact with a bottom of the hyper via (120, see below);
a connection via (120, see below) disposed in the one of the dielectric layers and in contact with a bottom of the metal plate; and
a first metal trench (120) in contact with a bottom of the connection via (see below),
wherein the first metal trench comprises:
a line portion (LP, see below) extending along a first direction (D1) and non-overlapping with the metal plate, and
a protruding portion (PP, see below) extending from the line portion along a second direction (D2) perpendicular to the first direction (D1) and overlapping with the metal plate.
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Chu does not teach the first metal trench is disposed in another one of the dielectric layers that is not the same dielectric layer in which the connection via and the metal plate is located. However, Chu teaches dielectric layer 100 is a backside distribution network ([0025]). That is, it is a backside metallization/interconnection layer. Interconnection layers are known to have multiple lines and vias formed in a damascene manner, which means layer 100 would be comprised of multiple dielectric layers.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed that layer 100 would be comprised of multiple dielectric layers so as to fabricate multiple interconnects.
Since the metal plate/connection via and the metal trench are at different levels, they would also be in different layers.
As to claim 20, Chu further teaches a second metal trench disposed adjacent to the first metal trench in the another one of the dielectric layers, wherein the bottom of the hyper via is non-overlapping with the second metal trench in a vertical direction perpendicular to a surface of the substrate (see fig. above).
Allowable Subject Matter
Claims 13-18 are allowed and claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 8, Chu further teaches another metal plate (310) disposed over and connected to the hyper via (421/422) but does not teach another dielectric layer disposed over the another metal plate and another hyper via extending vertically through the another dielectric layer and that is connected to the another metal plate.
As to claim 13, Chu teaches an interconnection structure (see annotated fig. 2B below), comprising:
a substrate (obvious if not inherent, this device is on a PCB or motherboard at a minimum, which would be a substrate);
a first metal trench disposed over the substrate (see below);
a second metal trench disposed adjacent to the first metal trench and in a same surface plane as the first metal trench (see below);
a metal plate comprising:
a first metal plate portion (PP1) overlapping the first metal trench and non-overlapping with the second metal trench, and
a second metal plate portion (PP2) overlapping the second metal trench and non-overlapping with the first metal trench;
a connection via extending between the first metal trench and the metal plate (see below);
at least one dielectric layer (200) disposed over the metal plate; and
a hyper via (421 and/or 422) penetrating the at least one dielectric layer ([0028]).
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Chu does not teach the hyper via extending to the first metal plate. The hyper via only extends to the first metal trench. Even if the metal trench was interpreted to be the first metal plate and vice versa, then the first metal trench would not have a second metal trench adjacent to and in the same plane as the first metal trench.
Claims 14-18 are allowed at least because they depend from allowed independent claim 13.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
7/16/26
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