DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-29 in the reply filed on January 21, 2026 is acknowledged. Claims 30-33 are withdrawn as they are directed to a nonelected invention.
Claim Objections
Claims 8-10 and 16-18 are objected to because of the following informalities.
These claims further limit layers by adding materials to a previously defined material layer. For example, Claim 1 states that “the channel protection layer includes carbon”. But Claim 8 states that “the channel protection layer includes silicon (Si), oxygen (O) and hydrogen (H)”. Therefore, Claim 8 may imply that the channel protection layer does not include carbon. It is recommended that the listed claims instead state “further includes”. With this change, Claim 8 would state “the channel protection layer further includes silicon (Si), oxygen (O) and hydrogen (H)”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 27, and 29 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Kishida et al. (“Kishida”), US 2015/0200113.
Regarding Claim 1, Kishida discloses a thin film transistor (100; Fig. 4; ¶ 0058-0059) comprising:
a base substrate (110; Fig. 4; ¶ 0057);
an oxide semiconductor layer (140; Fig. 4; ¶ 0065) on the base substrate (Fig. 4; ¶ 0065);
a channel protection layer (150; Fig. 4; ¶ 0068) in contact with the oxide semiconductor layer (Fig. 4; ¶ 0068 “channel protection layer 150 is formed on the oxide semiconductor layer 140”); and
a gate electrode (120; Fig. 4; ¶ 0061) spaced apart from the oxide semiconductor layer (¶ 0063 “gate insulating layer 130 is formed between the gate electrode 120 and the oxide semiconductor layer 140”) and at least partially overlapping with the oxide semiconductor layer (Fig. 4; ¶ 0065 “oxide semiconductor layer 140 is formed above the substrate 110 to face the gate electrode 120”),
wherein the channel protection layer includes carbon (¶ 0069).
Regarding Claim 27, Kishida discloses wherein the gate electrode is on the base substrate (Fig. 4; ¶ 0061 “gate electrode 120 is formed on the substrate 110”), and a gate insulation layer is on the gate electrode (Fig. 4; ¶ 0064 “gate insulating layer 130 is formed on the gate electrode 120”), and the channel protection layer is on the gate insulation layer (Fig. 4; ¶ 0068 “channel protection layer 150 is formed on…the gate insulating layer 130”).
Regarding Claim 29, Kishida discloses a display apparatus (Fig. 3; ¶ 0013 “a pixel circuit in the organic EL display device”) comprising the thin film transistor (100; Fig. 4; ¶ 0051, 0058-0059) of claim 1 (see the rejection of Claim 1 supra for the full mapping details related to 100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kishida et al. (“Kishida”), US 2015/0200113.
Regarding Claim 2 Kishida discloses wherein the channel protection layer includes silicon (Si) and oxygen (O) (¶ 0069 “channel protection layer 150 comprises… silicon, oxygen, and carbon; or a multi-layered film of the above”).
Kishida lacks specifically a concentration of the carbon is in a range between 1% and 10% by atom (at%) based on components of the channel protection layer.
MPEP 2144.05(I) is titled OVERLAPPING, APPROACHING, AND SIMILAR RANGES, AMOUNTS, AND PROPORTIONS and is directed to obviousness of claimed ranges.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida to have a concentration of the carbon is in a range between 1% and 10% by atom (at%) based on components of the channel protection layer because having a small amount of carbon inside would better manage heat in the thin film transistor and thereby enhance the reliability of the thin film transistor.
Regarding Claim 21, Kishida lacks specifically wherein the channel protection layer has a carbon (C) surface density fraction (C atoms/cm2) of 5.0 x 1015 or less:
a carbon (C) surface density fraction (C atoms/cm2) is calculated by a following equation:
Carbon (C) surface density fraction (C atoms/cm2) = surface density (total number of atoms/cm2) x carbon (C) concentration (C at%), and
the surface density means the surface density of the channel protection layer.
MPEP 2144.05(I) is titled OVERLAPPING, APPROACHING, AND SIMILAR RANGES, AMOUNTS, AND PROPORTIONS and is directed to obviousness of claimed ranges.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida to have wherein the channel protection layer has a carbon (C) surface density fraction (C atoms/cm2) of 5.0 x 1015 or less: a carbon (C) surface density fraction (C atoms/cm2) is calculated by a following equation: Carbon (C) surface density fraction (C atoms/cm2) = surface density (total number of atoms/cm2) x carbon (C) concentration (C at%), and the surface density means the surface density of the channel protection layer because having a small amount of carbon inside would better manage heat in the thin film transistor and thereby enhance the reliability of the thin film transistor.
Claims 3-7, 12, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Kishida et al. (“Kishida”), US 2015/0200113, in view of Hayashi, US 2017/0309649.
Regarding Claim 3, Kishida does not disclose wherein the channel protection layer is between the oxide semiconductor layer and the gate electrode.
Hayashi discloses wherein the channel protection layer (50; Fig. 9; ¶ 0129) is between (Fig. 9; ¶ 0133 “gate electrode 21 is disposed above the first oxide semiconductor layer 41 with the channel protection layer 50 being interposed in between”) the oxide semiconductor layer (41; Fig. 9; ¶ 0129) and the gate electrode (21; Fig. 9; ¶ 0129).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida to have wherein the channel protection layer is between the oxide semiconductor layer and the gate electrode, as taught by Hayashi, because “the mobility of the semiconductor layer can be adjusted extensively with accuracy” (Hayashi ¶ 0156).
Regarding Claim 4, Kishida as modified discloses wherein the channel protection layer is in contact with a side surface of the oxide semiconductor layer (Fig. 4 in this instance 150 is in contact with a side surface of 140; ¶ 0068).
Regarding Claim 5, Kishida as modified discloses wherein the channel protection layer surrounds an upper surface and a side surface of the oxide semiconductor layer (Fig. 4; ¶ 0068).
Regarding Claim 6, Kishida as modified discloses further comprising a buffer layer (130; Fig. 4; ¶ 0063) between the base substrate and the oxide semiconductor layer (Fig. 4 in this instance between 110 and 140; ¶ 0063), wherein the channel protection layer is in contact with a portion of the buffer layer (Fig. 4; ¶ 0063, 0065).
Regarding Claim 7, Kishida as modified discloses further comprising a gate insulating layer (130; Fig. 4; ¶ 0063) between the channel protection layer and the gate electrode (Fig. 4 in this instance gate insulating layer 130 is between 150 and 120).
Regarding Claim 12, Kishida as modified discloses wherein the channel protection layer is in contact with the gate electrode (Fig. 4 in this instance channel protection layer 150 is in indirect contact with gate electrode 120), and the channel protection layer has a thickness in a range between 10 nm and 100 nm (¶ 0068 “channel protection layer 150 has a film thickness of from 50 nm to 500 nm”).
Regarding Claim 28, Kishida does not disclose further comprising an etching barrier layer on the oxide semiconductor layer.
Hayashi discloses further comprising an etching barrier layer (50; Fig. 1; ¶ 0051 “an etch stopper layer”, ¶ 0053 in this instance the top silicon oxide film of the “three-layer laminated film”) on the oxide semiconductor layer (Fig. 1; ¶ 0050 “50 is disposed on” the first and second oxide semiconductor layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida to have further comprising an etching barrier layer on the oxide semiconductor layer, as taught by Hayashi, because the etching barrier layer “protects” the oxide semiconductor layer “from being etched when the respective source and drain electrodes” are formed (Hayashi ¶ 0051) thereby improving the performance and reliability of the thin film transistor.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kishida et al. (“Kishida”), US 2015/0200113, and Hayashi, US 2017/0309649, as applied to Claim 7, and further in view of Kim et al. (“Kim”), US 2022/0199829.
Regarding Claim 11, Kishida as modified discloses a thickness of the gate insulating layer of “50 nm to 300 nm” (¶ 0063).
Kishida as modified lacks wherein the channel protection layer has a thickness thinner than a thickness of the gate insulating layer, and the channel protection layer has a thickness in a range between 1nm and 10 nm.
Kim discloses wherein the channel protection layer has a thickness in a range between 1nm and 10 nm (¶ 0115 “140 may have a thickness of, for example, 1.2 nm to 2.5 nm” therefore the channel protection layer has a thickness thinner than a thickness of the gate insulating layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida as modified to have wherein the channel protection layer has a thickness thinner than a thickness of the gate insulating layer, and the channel protection layer has a thickness in a range between 1nm and 10 nm, ad taught by Kim, to improve the “electrical stability of the active layer” (Kim ¶ 0085) to improve the reliability of the thin film transistor (Kim ¶ 0085-0086). Therefore, Kishida as modified will have a channel protection layer of 1.2 to 2.5 nm and a gate insulating layer of “50 nm to 300 nm”. Thus, the gate insulating layer is thicker than the channel protection layer.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kishida et al. (“Kishida”), US 2015/0200113, in view of Yamazaki et al. (“Yamazaki”), US 2011/0084268.
Regarding Claim 13, Kishida does not disclose wherein the channel protection layer is between the oxide semiconductor layer and the base substrate.
Yamazaki discloses wherein the channel protection layer (204; Fig. 4C; ¶ 0121) is between (Fig. 4C) the oxide semiconductor layer (205; Fig. 4C; ¶ 0122) and the base substrate (200; Fig. 4C; ¶ 0112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida to have wherein the channel protection layer is between the oxide semiconductor layer and the base substrate, as taught by Yamazaki, because it allows the channel protection layer to function as “a protective layer” (Yamazaki ¶ 0121) to improve the reliability of the thin film transistor.
Regarding Claim 14, Kishida as modified does not disclose wherein the channel protection layer is in contact with an entire bottom surface of the oxide semiconductor layer.
Yamazaki discloses wherein the channel protection layer is in contact with an entire bottom surface of the oxide semiconductor layer (Fig. 4C; ¶ 0122 “Next, the semiconductor layer 205 is formed over…layer 204.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida as modified to have wherein the channel protection layer is in contact with an entire bottom surface of the oxide semiconductor layer, as taught by Yamazaki, because it allows the channel protection layer to function as “a protective layer” (Yamazaki ¶ 0121) to improve the reliability of the thin film transistor.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kishida et al. (“Kishida”), US 2015/0200113, and Yamazaki et al. (“Yamazaki”), US 2011/0084268, as applied to Claim 13, and further in view of Kim et al. (“Kim”), US 2022/0199829.
Regarding Claim 15, Kishida as modified does not disclose further comprising a buffer layer between the channel protection layer and the base substrate.
Kim discloses further comprising a buffer layer (125; Fig. 1; ¶ 0052) between (Fig. 1) the channel protection layer (140; Fig. 1; ¶ 0048) and the base substrate (110; Fig. 1; ¶ 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida as modified to have further comprising a buffer layer between the channel protection layer and the base substrate, as taught by Kim, because it allows the buffer layer to protect the oxide semiconductor layer (Kim ¶ 0052, 0178) to improve the reliability of the thin film transistor.
Claims 22-26 are rejected under 35 U.S.C. 103 as being unpatentable over Kishida et al. (“Kishida”), US 2015/0200113, in view of Yamazaki et al. (“Yamazaki ‘153”), US 2013/0187153.
Regarding Claim 22, Kishida does not disclose wherein the channel protection layer includes a first channel protection layer and a second channel protection layer, and the oxide semiconductor layer is between the first channel protection layer and the second channel protection layer.
Yamazaki ‘153 discloses wherein the channel protection layer includes a first channel protection layer (104b; Fig. 1C; ¶ 0043) and a second channel protection layer (107; Fig. 1C; ¶ 0044), and the oxide semiconductor layer (105; Fig. 1C; ¶ 0044) is between the first channel protection layer and the second channel protection layer (Fig. 1C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida to have wherein the channel protection layer includes a first channel protection layer and a second channel protection layer, and the oxide semiconductor layer is between the first channel protection layer and the second channel protection layer, as taught by Yamazaki ‘153, in order to improve the reliability of the thin film transistor (Yamazaki ‘153 ¶ 0102).
Regarding Claim 23, Kishida as modified does not disclose wherein the first channel protection layer is in contact with a lower surface of the oxide semiconductor layer, and the second channel protection layer is in contact with an upper surface of the oxide semiconductor layer.
Yamazaki ‘153 discloses wherein the first channel protection layer is in contact with a lower surface of the oxide semiconductor layer (Fig. 1C), and the second channel protection layer is in contact with an upper surface of the oxide semiconductor layer (Fig. 1C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida as modified to have wherein the first channel protection layer is in contact with a lower surface of the oxide semiconductor layer, and the second channel protection layer is in contact with an upper surface of the oxide semiconductor layer, as taught by Yamazaki ‘153, in order to improve the reliability of the thin film transistor (Yamazaki ‘153 ¶ 0102).
Regarding Claim 24, Kishida as modified does not disclose at least one of the first channel protection layer and the second channel protection layer is in contact with a side surface of the oxide semiconductor layer, and at least a part of the first channel protection layer and at least a part of the second channel protection layer are in contact with each other.
Yamazaki ‘153 discloses at least one of the first channel protection layer and the second channel protection layer is in contact with a side surface of the oxide semiconductor layer, and at least a part of the first channel protection layer and at least a part of the second channel protection layer are in contact with each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida as modified to have at least one of the first channel protection layer and the second channel protection layer is in contact with a side surface of the oxide semiconductor layer, and at least a part of the first channel protection layer and at least a part of the second channel protection layer are in contact with each other, as taught by Yamazaki ‘153, in order to improve the reliability of the thin film transistor (Yamazaki ‘153 ¶ 0102).
Regarding Claim 25, Kishida as modified does not disclose further comprising a buffer layer between the first channel protection layer and the base substrate.
Yamazaki ‘153 discloses further comprising a buffer layer (102; Fig. 1C; ¶ 0043) between (Fig. 1C) the first channel protection layer and the base substrate (101; Fig. 1C; ¶ 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida as modified to have further comprising a buffer layer between the first channel protection layer and the base substrate, as taught by Yamazaki ‘153, in order to improve the reliability of the thin film transistor (Yamazaki ‘153 ¶ 0076).
Regarding Claim 26, Kishida as modified does not disclose further comprising a gate insulating layer between the second channel protection layer and the gate electrode.
Yamazaki ‘153 discloses further comprising a gate insulating layer (104a; Fig. 1C; ¶ 0043) between (Fig. 1C) the second channel protection layer and the gate electrode (103; Fig. 1C; ¶ 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kishida as modified to have further comprising a gate insulating layer between the second channel protection layer and the gate electrode, as taught by Yamazaki ‘153, in order to improve the reliability of the thin film transistor (Yamazaki ‘153 ¶ 0102).
Allowable Subject Matter
Claims 8-10 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 8, the prior art does not teach or render obvious wherein the channel protection layer includes silicon (Si), oxygen (O) and hydrogen (H), the gate insulating layer includes silicon (Si), oxygen (O) and hydrogen (H), and a hydrogen concentration (at %) of the channel protection layer is lower than a hydrogen concentration (at %) of the gate insulating layer. Therefore, the combination of the features of Claims 1, 3, 7, and 8 is considered allowable.
Claims 9-10 incorporate all of the limitations of allowable Claim 8. Therefore, it is also allowable.
Regarding Claim 16, the prior art does not teach or render obvious wherein the channel protection layer includes silicon (Si), oxygen (O) and hydrogen (H), the buffer layer includes silicon (Si), oxygen (O) and hydrogen (H), and a hydrogen concentration (at %) of the channel protection layer is lower than the hydrogen concentration (at %) of the buffer layer. Therefore, the combination of Claims 1, 13, 15, and 16 is considered allowable.
Regarding Claim 17, the prior art does not teach or render obvious wherein the buffer layer includes carbon (C), and a carbon concentration (at %) of the channel protection layer is 100 times or more of the carbon concentration (at %) of the buffer layer. Therefore, the combination of Claims 1, 13, 15, and 17 is considered allowable.
Regarding Claim 18, the prior art does not teach or render obvious wherein the channel protection layer includes Non Bonding Oxygen (NBO), the buffer layer includes Non Bonding Oxygen (NBO) and a density of the Non Bonding Oxygen (NBO) of the channel protection layer is lower than a density of the Non Bonding Oxygen (NBO) of the buffer layer. Therefore, the combination of Claims 1, 13, 15, and 18 is considered allowable.
Regarding Claim 19, the prior art does not teach or render obvious wherein the channel protection layer has a thickness thinner than a thickness of the buffer layer, and the channel protection layer has a thickness in a range between 1 nm and 10 nm. Therefore, the combination of Claims 1, 13, 15, and 19 is considered allowable.
Regarding Claim 20, the prior art does not teach or render obvious wherein the channel protection layer is in contact with the base substrate, and the channel protection layer has a thickness in a range between 10 nm and 100 nm. Therefore, the combination of Claims 1, 13, and 20 is considered allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamazaki, US 2017/0352763, discloses a thin film transistor with an oxide semiconductor layer and a channel protection layer in contact with the oxide semiconductor layer. Nonoguchi et al., US 2016/0254280, discloses a thin film transistor with an oxide semiconductor layer and a channel protection layer in contact with the oxide semiconductor layer. Morosawa et al., US 2011/0140116, discloses a thin film transistor with an oxide semiconductor layer and a channel protection layer in contact with the oxide semiconductor layer.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818