Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements filed 9/6/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 9/6/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Han et al. (U.S. Patent Publication No. 2010/0148314).
Referring to figures 1-5, Han et al. teaches a substrate comprising:
chip areas (12);
a first scribe lane (11) disposed between the chip areas; and
a first trench pattern (75) disposed in the first scribe lane (11), wherein the first scribe lane extends in a first direction, and the first trench pattern includes a plurality of first trench groups spaced apart from each other in the first direction (see figures 1-2).
Regarding to claim 2, wherein each of the first trench groups includes a plurality of first trenches extending in the first direction (see figures 1-2).
Regarding to claim 3, the plurality of first trenches have segments shapes parallel with each other in a top view (see figures 1-2).
Regarding to claim 4, the first trenches may be arranged off-set in a second direction, and the first direction is perpendicular to the second direction (see figures 1-2).
Regarding to claim 5, a second scribe lane disposed between the chip areas; and a second trench pattern disposed in the second scribe lane, wherein: the second scribe lane extends in the second direction, the first direction is perpendicular to the second direction, and the second trench pattern includes a plurality of second trenches extending in the second direction (see figure 1, the horizontal scribe lane is the first direction, the vertical scribe lane is the second direction).
Regarding to claim 6, the second trench pattern includes a plurality of second trench groups spaced apart from each other in the second direction, and each of the plurality of second trench groups includes the plurality of second trenches (see figures 1-3).
Regarding to claim 7, a cross-intersection area where the first scribe lane and the second scribe lane cross each other; and a cross-intersection trench pattern disposed in the cross-intersection area (11, see figure 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-9, 11, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (U.S. Patent Publication No. 2010/0148314) applied in claim(s) 1-7 above in view of Huang et al. (U.S. Patent Publication No. 2023/0402406).
Referring to figures 1-5, Han et al. teaches a wafer comprising: a substrate including
chip areas (12) and scribe lane (11) between the chip areas; and
a first trench pattern (75) disposed in the first scribe lane (11), wherein the first scribe lane extends in a first direction, and the first trench pattern includes a plurality of first trench groups spaced apart from each other in the first direction (see figures 1-2).
However, the reference does not clearly teach dummy top metal patterns over the dummy metal patterns; a redistribution insulating layer over the dummy top metal patterns; and a plurality of trenches vertically passing through the redistribution insulating layer, wherein the plurality of trenches vertically overlap with the dummy metal patterns and the dummy top metal patterns.
Huang et al. dummy top metal patterns (270) over the dummy metal patterns (270); a redistribution insulating layer (the layer between layer 340) over the dummy top metal patterns; and a plurality of trenches vertically passing through the redistribution insulating layer, wherein the plurality of trenches vertically overlap with the dummy metal patterns and the dummy top metal patterns (see figure 3, meeting claim 11), each of the chip areas (210-211) includes: metal patterns (310/320) over the substrate; top metal patterns (top 330) over the metal patterns; redistribution insulating layers (the layer between layer 340) over the top metal patterns: a redistribution via hole vertically passing through the redistribution insulating layer and exposing a surface of a portion of the top metal patterns; a redistribution via metal layer (340) on an inner wall of the redistribution via hole and over the exposed surface of the top metal patterns; and a redistribution layer (the metal on top of layer 340) disposed over the redistribution insulating layer (see figure 3, meeting claims 11, 14).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a barrier guard ring pattern disposed in the first scribe lane to be adjacent to the chip areas; and a barrier trench disposed in the first scribe lane to be vertically aligned with the barrier guard ring pattern, dummy metal patterns disposed in the first scribe lane to be vertically aligned with the first trench pattern; an interlayer insulating layer surrounding the dummy metal patterns; dummy top metal patterns disposed over the dummy metal patterns and the interlayer insulating layer; and a passivation layer surrounding the dummy top metal patterns in Han et al. as taught by Huang et al. because it is known in the semiconductor art to improve reliability by reducing parasitic effects.
However, the reference does not clearly teach a barrier guard ring pattern disposed in the first scribe lane to be adjacent to the chip areas; and a barrier trench disposed in the first scribe lane to be vertically aligned with the barrier guard ring pattern (in claim 8), dummy metal patterns disposed in the first scribe lane to be vertically aligned with the first trench pattern; an interlayer insulating layer surrounding the dummy metal patterns; dummy top metal patterns disposed over the dummy metal patterns and the interlayer insulating layer; and a passivation layer surrounding the dummy top metal patterns (in claim 9).
Huang et al. teaches a semiconductor device having a barrier guard ring pattern (270) disposed in the first scribe lane (240) to be adjacent to the chip areas (250); and a barrier trench disposed in the first scribe lane to be vertically aligned with the barrier guard ring pattern (see figures 2-3, meeting claim 8), dummy metal patterns (450) disposed in the first scribe lane (240) to be vertically aligned with the first trench pattern; an interlayer insulating layer (330) surrounding the dummy metal patterns; dummy top metal patterns(340) disposed over the dummy metal patterns (450) and the interlayer insulating layer (330); and a passivation layer surrounding the dummy top metal patterns (layer on top of 220, see figures 2-3, meeting claim 9).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a barrier guard ring pattern disposed in the first scribe lane to be adjacent to the chip areas; and a barrier trench disposed in the first scribe lane to be vertically aligned with the barrier guard ring pattern, dummy metal patterns disposed in the first scribe lane to be vertically aligned with the first trench pattern; an interlayer insulating layer surrounding the dummy metal patterns; dummy top metal patterns disposed over the dummy metal patterns and the interlayer insulating layer; and a passivation layer surrounding the dummy top metal patterns in Han et al. as taught by Huang et al. because it is known in the semiconductor art to improve reliability by reducing parasitic effects.
Claim 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (U.S. Patent Publication No. 2010/0148314) in view of Huang et al. (U.S. Patent Publication No. 2023/0402406) applied in claim(s) 11, 14 above, and further in view of Han et al. (U.S. Patent Publication No. 2019/0035750).
Referring to figures 1-5, Han et al. teaches a wafer comprising: a substrate including
chip areas (12) and scribe lane (11) between the chip areas; and
a first trench pattern (75) disposed in the first scribe lane (11), wherein the first scribe lane extends in a first direction, and the first trench pattern includes a plurality of first trench groups spaced apart from each other in the first direction (see figures 1-2).
However, the reference does not clearly teach a capping insulating layer formed on the inner walls of the trenches.
Han et al. teaches a capping insulating layer (145) formed on the inner walls of the trenches (see figure 5G).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a capping insulating layer formed on the inner walls of the trenches in Han et al. as taught by Han et al. because forming a capping insulating layer is known in the semiconductor to protect the device.
Allowable Subject Matter
Claims 10, 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the prior art teaches or suggests air gaps between the dummy top metal patterns, and wherein the air gaps are defined by the passivation layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893