Attorney’s Docket Number: 8054S-1693 (AZ1117US)
Filing Date: 09/06/2023
Claimed Priority Date: 09/30/2022 (KR10-2022-0125042)
Applicant: Kim et al
Examiner: Aneesa Baig
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18461569 filed on 09/06/2023 has been entered. Pending in this Office Action are claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 2, 8, 11, 12, 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park e al (US20210257275, Hereinafter Park) in view of Aleksov et al (US 20160086905 A1, Hereinafter Aleksov).
Regarding claim 1, Park (e.g., Fig 1 [0001]-[0059][0037]) shows most aspects of the invention, including a semiconductor package, comprising:
a package substrate (100);
an interposer including a substrate (an interposer layer 200 with a substrate layer 212), a wiring layer (redistribution layer 220), first bonding pads (redistribution pads 246), second bonding pads (connection pads 206), and first conductive bumps (112), Wherein the substrate has a plurality of through electrodes formed to penetrate therethrough (216), wherein the wiring layer is provided on an upper surface of the substrate and has a plurality of wirings electrically connected to the plurality of through electrodes, wherein the first bonding pads are provided on the wiring layer and are electrically connected to the plurality of wirings ( Fig 1 shows 220 on top of the substrate), wherein the second bonding pads are provided on a lower surface of the substrate and are electrically connected to the plurality of through electrodes (206 is on the bottom surface of the substrate), wherein the first conductive bumps are disposed on the second bonding pads, respectively, wherein the interposer is mounted on the package substrate via the first conductive bumps (112 connects the substrate to the interposer [0037]);
first and second semiconductor devices provided on the interposer and spaced apart from each other (318,328,338), wherein front surfaces of each of the first and second semiconductor devices, on which chip pads ( first chip pads 316 [0055]) are disposed, face the interposer, and wherein the first and second semiconductor devices are mounted on the interposer via second conductive bumps (312), that are disposed on the chip pads , respectively;
a sealing member disposed on the interposer and covering the first and second semiconductor devices (molding layer 300 [0057]); and
an underfill member filling a space between the first conductive bumps that are between the package substrate and the interposer (underfill material 114),
While Park shows multiple conductive bumps under the interposer connected to bonding pads, it does not show the bump regions to have a different inner and outer region with varying shapes. Aleksov, (e.g., Fig 4-11, Abstract, [0013]-[0030]) on the other hand and in a related field of connecting bumps between two microelectronic devices, teaches bumps placed in a inner and outer region of a microelectronic substrate ( Fig 8, [0015][0024]) where the inner bumps (1201) are circular, while the outer bumps (150, Figs 8 and 9) are oval, and where an axis (NP) extends toward a center of the device.
Aleksov also teaches that the inner bumps may be less susceptible to solder joint failure due to their location and size while the bumps closer to the periphery may be more prone to solder joint failure. The oval shapes around the periphery solve this issue as the solder volume in the substantially oval solder bumps 150 is greater along the radial vectors 160 which is also the primary direction of stress. Hence the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stress between two microelectronic surfaces.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the oval shaped and circular bumps on pillars in between the interposer and substrate in the package of Park, as taught by Aleksov to reduce solder joint failure due to stress.
Regarding Claim 2, See comments from paragraph 2-5 of claim 1, as they would be considered repeated here.
Regarding Claim 8, Park shows the protective layer (first passivation layer 204 [0043]) on the lower surface of the interposer has openings for the second bonding pads (connection pads 206).
Regarding claim 11, Park (e.g., Fig 1 [0001]-[0059][0037]) shows most aspects of the invention, including a semiconductor package, comprising:
a package substrate (100);
an interposer (an interposer layer 200 with a substrate layer 212) mounted on the package substrate via first conductive bumps (112):
first and second semiconductor devices disposed spaced apart from each other on the interposer (318,328,338), and mounted on the interposer via second conductive bumps (312); and
an underfill member (114) filling a space between the first conductive bumps that are disposed between the package substrate and the interposer
While Park shows multiple conductive bumps under the interposer connected to bonding pads, it does not show the bump regions to have a different inner and outer region with varying shapes. Aleksov, (e.g., Fig 4-11, Abstract, [0013]-[0030]) on the other hand and in a related field of connecting bumps between two microelectronic devices, teaches bumps placed in an inner and outer region of a microelectronic substrate ( Fig 8, [0015][0024]) where the inner bumps (1201) are circular, while the outer bumps (150, Figs 8 and 9) are oval, and where an axis (NP) extends toward a center of the device.
Aleksov also teaches that the inner bumps may be less susceptible to solder joint failure due to their location and size while the bumps closer to the periphery may be more prone to solder joint failure. The oval shapes around the periphery solve this issue as the solder volume in the substantially oval solder bumps 150 is greater along the radial vectors 160 which is also the primary direction of stress. Hence the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stress between two microelectronic surfaces.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the oval shaped and circular bumps on pillars in between the interposer and substrate in the package of Park, as taught by Aleksov to reduce solder joint failure due to stress.
Regarding Claim 12, Park shows
a substrate (200) having a plurality of through electrodes formed to penetrate therethrough;
a wiring layer (220) disposed on an upper surface of the substrate and having a plurality of wirings electrically connected to the plurality of through electrodes (216):
first bonding pads (redistribution pads 246), provided on the wiring layer and electrically connected to the plurality of wirings;
the second bonding pads (connection pads 206), provided on a lower surface of the substrate and electrically connected to the plurality of through electrodes; and
the first conductive bumps respectively disposed on the second bonding pads (112).
Regarding Claim 13, Park shows the protective layer (first passivation layer 204 [0043]) on the lower surface of the interposer has openings for the second bonding pads (connection pads 206).
Regarding Claim 15, See comments from paragraph 8-11 of claim 11, as they would be considered repeated here.
Claim 1,5,10,11,18 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Pham et al (US 20080185735 A1, Hereinafter Pham).
Regarding claim 1, Park (e.g., Fig 1 [0001]-[0059][0037]) shows most aspects of the invention, including a semiconductor package, comprising:
a package substrate (100);
an interposer including a substrate (an interposer layer 200 with a substrate layer 212), a wiring layer (redistribution layer 220), first bonding pads (redistribution pads 246), second bonding pads (connection pads 206), and first conductive bumps (112), Wherein the substrate has a plurality of through electrodes formed to penetrate therethrough (216), wherein the wiring layer is provided on an upper surface of the substrate and has a plurality of wirings electrically connected to the plurality of through electrodes, wherein the first bonding pads are provided on the wiring layer and are electrically connected to the plurality of wirings () Fig 1 shows 220 on top of the substrate), wherein the second bonding pads are provided on a lower surface of the substrate and are electrically connected to the plurality of through electrodes (206 is on the bottom surface of the substrate), wherein the first conductive bumps are disposed on the second bonding pads, respectively, wherein the interposer is mounted on the package substrate via the first conductive bumps (112 connects the substrate to the interposer [0037]);
first and second semiconductor devices provided on the interposer and spaced apart from each other (318,328,338), wherein front surfaces of each of the first and second semiconductor devices, on which chip pads ( first chip pads 316 [0055]) are disposed, face the interposer, and wherein the first and second semiconductor devices are mounted on the interposer via second conductive bumps that are disposed on the chip pads (312), respectively;
a sealing member disposed on the interposer and covering the first and second semiconductor devices (molding layer 300 [0057]); and
an underfill member filling a space between the first conductive bumps that are between the package substrate and the interposer (underfill material 114),
While Park shows multiple conductive bumps under the interposer connected to bonding pads, it does not show the bump regions to have a different inner and outer region with varying shapes. Pham (e.g., Fig 7-9, [0025]-[0036]), on the other hand and in a related field of BGA connections, teaches bond pad with conductive bumps which are circular in an inner region, and elliptical shaped around the periphery of the region. Pham teaches that as the bond pads around the periphery are elongated along a axis stemming radially from the center and the dimensions of solder joints formed to these bond pads will be greatest along the axes of greatest CTE differential stress. Since solder joint failures occur most frequently near the bond pad/solder joint interface, this approach has the effect of increasing the dimensions of the bond pad and/or the corresponding solder mask opening, and hence the size and strength of the solder joint, in the direction most needed ([0030]).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the oval shaped and circular bumps on pillars in between the interposer and substrate in the package of Park, as taught by Pham, to for bump connections that are more resistant to stress and strain, and that exhibit improved lifetimes ([0006]).
Regarding Claim 5, Park shows several bumps, but is silent in regards to the width of elliptical bumps. Pham, on the other hand and in a related field, teaches first bump pads with a diameter of 85 um, and second bump pads with a long axis length of 106.4 microns, and a short axis length of 85 um. Pham also teaches that the dimensions of the solder joints may be similar.
Accordingly, the specific claimed width and length of the bumps, absent any criticality, is only considered to be the “optimum” dimensions of bump that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired the desired package dimensions, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the ratio of the width and length of the elliptical bumps are maintained, as already suggested by Pham.
Since the applicant has not established the criticality (see next paragraph below) of the claimed proportion, it would have been obvious to one of ordinary skill in the art to use the claimed values in the structure of Park.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 10, while Park shows several pads, it is silent in regards to the width of circular and elliptical pads. Pham, on the other hand and in a related field, teaches first bump pads with a diameter of 85 um, and second bump pads with a long axis length of 106.4 microns, and a short axis length of 85 um, which falls outside of the range of 5-40um.
However, the specific claimed width and length of the bumps, specifically the width of 5-40um absent any criticality, is only considered to be the “optimum” dimensions of bump that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired package dimensions manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the ratio of the width and length of the elliptical bumps are maintained, as already suggested by Pham.
Since the applicant has not established the criticality (see next paragraph below) of the claimed proportion, it would have been obvious to one of ordinary skill in the art to use the claimed values in the structure of Park.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 11, Park (e.g., Fig 1 [0001]-[0059][0037]) shows most aspects of the invention, including a semiconductor package, comprising:
a package substrate (100);
an interposer (an interposer layer 200 with a substrate layer 212) mounted on the package substrate via first conductive bumps (112):
first and second semiconductor devices disposed spaced apart from each other on the interposer (318,328,338), and mounted on the interposer via second conductive bumps (312); and
an underfill member (114) filling a space between the first conductive bumps that are disposed between the package substrate and the interposer
While Park shows multiple conductive bumps under the interposer connected to bonding pads, it does not show the bump regions to have a different inner and outer region with varying shapes.
Pham (e.g., Fig 7-9, [0025]-[0036]), on the other hand and in a related field of BGA connections, teaches bond pad with conductive bumps which are circular in an inner region, and elliptical shaped around the periphery of the region. Pham teaches that as the bond pads around the periphery are elongated along a axis stemming radially from the center and the dimensions of solder joints formed to these bond pads will be greatest along the axes of greatest CTE differential stress. Since solder joint failures occur most frequently near the bond pad/solder joint interface, this approach has the effect of increasing the dimensions of the bond pad and/or the corresponding solder mask opening, and hence the size and strength of the solder joint, in the direction most needed ([0030]).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the oval shaped and circular bumps on pillars in between the interposer and substrate in the package of Park, as taught by Pham, to for bump connections that are more resistant to stress and strain, and that exhibit improved lifetimes ([0006]).
Regarding Claim 18, See comments from paragraph 19-23 of claim 5, as they would be considered repeated here.
Claim 6, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Aleksov further in view of Cheng (US 20110101527 A1, Hereinafter Cheng).
Regarding Claim 6, While Park in view of Aleksov shows a copper pillar with bump, both are silent in regards to the overall thickness withing a range of 10-100um.
Cheng (Fig 2D, 1C, [0025]-[0028]), on the other hand and in a related field of pillar bumps teaches bumps that have a pillar height of about 5-100 um or about 40.about.70 um and a cap solder layer of about 1-5um, hence within the range of 10-100um.
However, the height range of the bumps, absent any criticality, is only considered to be the “optimum” dimensions of a bump that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the desired package dimensions, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the bump and pillar combination is formed, as already suggested by Aleksov and Cheng.
Since the applicant has not established the criticality (see next paragraph below) of the claimed proportion, it would have been obvious to one of ordinary skill in the art to use the claimed values in the structure of Park.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 19, See comments from paragraph 35-41 of claim 6, as they would be considered repeated here.
Claim 9, 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Aleksov further in view of Huang et al (US 20160086905 A1, Hereinafter Huang).
Regarding Claim 9, while Park shows a protective layer around the second bonding pads, it does not show the layer to include PIDS.
Huang, on the other hand and in a related field of passivation, teaches a polyimide (120, Fig 1E [0019]) that includes photosensitive chemical such that it can be simply patterned to create openings in the UBM regions by a lithography process without etch.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have used PIDs as the protective layer around the second bonding pads to reduce processing steps and increase throughput of the manufacturing process.
Regarding Claim 14, See comments from paragraph 43-45 of claim 9, as they would be considered repeated here.
Allowable Subject Matter
Claim 3,4,16,17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANEESA RIAZ BAIG/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814