DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-9, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210366846 (Hung et al) in view of US 20230069107 (Wei).
Concerning claim 1, Hung discloses a semiconductor integrated circuit (IC) device comprising (Figs.2A-5B): a handler semiconductor IC device comprising (Figs. 3A and 3B): a handler substrate (301), a diode doped region (302/304) in the handler substrate (Fig. 3B). . . and an active semiconductor IC device comprising (Figs. 2A and 2B): a backside source/drain (S/D) contact (504) connected to a S/D region (205); a backside diode contact (504) electrically connected to the diode doped region (Figs. 5A-5B and [0040], note that the contacts 504 are provided on the left and right side of the device and that they are electrically connected to each of these features).
Hung does not disclose that the handler substrate additionally includes an interlayer dielectric (ILD) layer is formed over the handler substrate; and a diode contact in the ILD layer and extending through the ILD layer to electrically contact the diode doped region. However, Wei discloses an integrated circuit configuration (Figs. 3A-3C) in which a handler substrate (25); a diode doped region (130) in the handler substrate ([0026]); an interlayer dielectric (ILD) layer (126) is formed over the handler substrate ([0025]); and a diode contact (124) in the ILD layer and extending through the ILD layer to electrically contact the diode doped region ([0025]). Wei discloses that techniques are provided to fabricate a carrier substrate that includes integrated junction regions along with conductive surface contacts that can be used to provide a discharge pathway to ground for plasma-induced charge that arises during backside processing, thereby reducing the risk of ESD damage to the conductive features from the interconnect region and device region of the integrated circuit ([0014]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the handler substrate of Hung to include an interlayer dielectric (ILD) layer is formed over the handler substrate; and a diode contact in the ILD layer and extending through the ILD layer to electrically contact the diode doped region as disclosed by Wei in order to reduce the risk of ESD damage to the conductive features from the interconnect region and device region of the integrated circuit.
Continuing to claim 2, Hung in view of Wei discloses wherein the active semiconductor IC device further comprises a frontside back end of line (BEOL) network with a charge collector wire (Hung 210) connected to the diode doped region (Hung [0021]).
Considering claim 4, Hung in view of Wei discloses wherein the active semiconductor IC device further comprises a frontside S/D contact (Hung 208) connected to the diode doped region through the charge collector wire (Hung Fig. 2B).
Referring to claim 5, Hung in view of Wei discloses wherein the active semiconductor IC device further comprises a first contact pad (Hung 216/222) connected to the charge collector wire (Hung Figs. 2A-2B and [0022]-[0023]).
Regarding claim 6, Hung in view of Wei discloses wherein the handler semiconductor IC device further comprises a second contact pad (Hung 316/322) connected to the diode doped region (Hung Figs. 3A-3B and [0031]).
Pertaining to claim 7, Hung in view of Wei discloses wherein electrical charge within the charge collector flows in a direction towards and dissipates through the diode doped region (Hung [0027]-[0029]).
As to claim 8, Hung in view of Wei discloses wherein the active semiconductor IC device further comprises
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an electrical pathway (Hung annotated Fig. 5B above illustrates an arrow representing the metal connections that form an electrical pathway from the charge collector wire (Hung 210) to the first contact pad (Hung 222)) connected to the charge collector wire and connected to the first contact pad, the electric pathway comprising a plurality of conductive wires and a plurality of conductive vias (Hung [0022]-[0023]).
Concerning claim 9, Hung in view of Wei discloses wherein the handler semiconductor IC device further comprises a diode contact between the second contact pad and the diode doped region (Hung Fig. 5B and [0032], note that the feature 322 has a vertical and horizontal components and the examiner is interpreting the horizontal component as the second pad and the vertical portion is the diode contact between the second contact pad and the diode doped region).
Continuing to claim 19, Hung discloses a semiconductor integrated circuit (IC) device fabrication method comprising: bonding a handler semiconductor IC device (Figs. 3A-3B) to an active semiconductor device (Figs. 2A-2B and Fig. 4B); a handler semiconductor IC device comprises (Figs. 3A and 3B): a handler substrate (301), a diode doped region (302/304) in the handler substrate (Fig. 3B). . . forming a backside back end of line (BEOL) network over a backside of the active semiconductor device (Fig. 5A-5B and [0039]-[0040]); and dissipating electrical charge through a frontside BEOL network of the active semiconductor device and further through the handler semiconductor IC device ([0040]-[0041]).
Hung does not disclose that the handler substrate additionally includes an interlayer dielectric (ILD) layer is formed over the handler substrate; and a diode contact in the ILD layer and extending through the ILD layer to electrically contact the diode doped region. However, Wei discloses an integrated circuit configuration (Figs. 3A-3C) in which a handler substrate (25); a diode doped region (130) in the handler substrate ([0026]); an interlayer dielectric (ILD) layer (126) is formed over the handler substrate ([0025]); and a diode contact (124) in the ILD layer and extending through the ILD layer to electrically contact the diode doped region ([0025]). Wei discloses that techniques are provided to fabricate a carrier substrate that includes integrated junction regions along with conductive surface contacts that can be used to provide a discharge pathway to ground for plasma-induced charge that arises during backside processing, thereby reducing the risk of ESD damage to the conductive features from the interconnect region and device region of the integrated circuit ([0014]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the handler substrate of Hung to include an interlayer dielectric (ILD) layer is formed over the handler substrate; and a diode contact in the ILD layer and extending through the ILD layer to electrically contact the diode doped region as disclosed by Wei in order to reduce the risk of ESD damage to the conductive features from the interconnect region and device region of the integrated circuit.
Referring to claim 20, Hung in view of Wei discloses wherein the electrical charge is dissipated through a diode doped region (Hung 302/304) within the handler semiconductor IC device (Hung [0027]-[0029]).
Claim(s) 10, 11, and 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210366846 (Hung et al) in view of US 20230069107 (Wei) and US 20220293597 (Hu et al).
Regarding claim 10, Hung discloses a semiconductor integrated circuit (IC) device comprising (Figs. 2A-5B): an . . . diode within a handler semiconductor IC device (Figs. 3A and 3B):, the . . .diode comprising: a handler substrate (301), and a diode doped region (302/304) in the handler substrate (Fig. 3B). . . and an active semiconductor IC device comprising (Figs. 2A and 2B): a backside source/drain (S/D) contact (504) connected to a S/D region (205); a backside diode contact (504) electrically connected to the diode doped region (Figs. 5A-5B and [0040], note that the contacts 504 are provided on the left and right side of the device and that they are electrically connected to each of these features).
Hung does not disclose that the diode is an antenna diode or that the handler substrate additionally includes an interlayer dielectric (ILD) layer is formed over the handler substrate; and a diode contact in the ILD layer and extending through the ILD layer to electrically contact the diode doped region. However, Wei discloses an integrated circuit configuration (Figs. 3A-3C) in which a handler substrate (25); a diode doped region (130) in the handler substrate ([0026]); an interlayer dielectric (ILD) layer (126) is formed over the handler substrate ([0025]); and a diode contact (124) in the ILD layer and extending through the ILD layer to electrically contact the diode doped region ([0025]). Wei discloses that techniques are provided to fabricate a carrier substrate that includes integrated junction regions along with conductive surface contacts that can be used to provide a discharge pathway to ground for plasma-induced charge that arises during backside processing, thereby reducing the risk of ESD damage to the conductive features from the interconnect region and device region of the integrated circuit ([0014]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the handler substrate of Hung to include an interlayer dielectric (ILD) layer is formed over the handler substrate; and a diode contact in the ILD layer and extending through the ILD layer to electrically contact the diode doped region as disclosed by Wei in order to reduce the risk of ESD damage to the conductive features from the interconnect region and device region of the integrated circuit.
Additionally, Hu discloses some IC manufacturing processes, may cause electric charges to accumulate in areas having been subject to these processes. The die-to-die interconnect, being conductive, may therefore accumulate electric charges during manufacturing. It is not uncommon that the die-to-die interconnect, which may accumulate a large amount of charges, is directly connected to the gate dielectric; therefore, the gate dielectric may run the risk of breaking down by these charges. Hence, it is advantageous to protect the gate dielectric that is directly connected to the die-to-die interconnect from these charges, or PID. One way to provide such PID protection is to introduce an antenna diode to the circuit ([0035]-[0037]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the diode within the handler substrate of Hung to be an antenna diode in order to provide PID protection to the device as disclosed by Hu.
Pertaining to claim 11, Hung in view of Wei and Hu discloses wherein the active semiconductor IC device further comprises a frontside back end of line (BEOL) network with a charge collector wire (Hung 210) connected to the diode doped region (Hung [0021]).
As to claim 13, Hung in view of Wei and Hu discloses wherein the active semiconductor IC device further comprises a frontside S/D contact (Hung 208) connected to the diode doped region through the charge collector wire (Hung Fig. 2B).
Concerning claim 14, Hung in view of Wei and Hu discloses wherein the active semiconductor IC device further comprises a first contact pad (Hung 216/222) connected to the charge collector wire (Hung Figs. 2A-2B and [0022]-[0023]).
Continuing to claim 15, Hung in view of Wei and Hu discloses wherein the handler semiconductor IC device further comprises a second contact pad (Hung 316/322) connected to the diode doped region (Hung Figs. 3A-3B and [0031]).
Considering claim 16, Hung in view of Wei and Hu discloses wherein electrical charge within the charge collector flows in a direction towards and dissipates through the antenna diode (Hung [0027]-[0029]).
Referring to claim 17, Hung in view of Wei and Hu discloses wherein the active semiconductor IC device further comprises
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an electrical pathway (Hung annotated Fig. 5B above illustrates an arrow representing the metal connections that form an electrical pathway from the charge collector wire (210) to the first contact pad (222)) connected to the charge collector wire and connected to the first contact pad, the electric pathway comprising a plurality of conductive wires and a plurality of conductive vias (Hung [0022]-[0023]).
Regarding claim 18, Hung in view of Wei and Hu discloses wherein the handler semiconductor IC device further comprises a diode contact between the second contact pad and the diode doped region (Hung Fig. 5B and [0032], note that the feature 322 has a vertical and horizontal components and the examiner is interpreting the horizontal component as the second pad and the vertical portion is the diode contact between the second contact pad and the diode doped region).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210366846 (Hung et al) in view of US 20230069107 (Wei) as applied to claim 1 above, and further in view of US 7816231 (Dyer et al).
Pertaining to claim 3, Hung in view of Wei discloses forming frontside contacts (208).
Hung in view of Wei does not disclose wherein the active semiconductor IC device further comprises a frontside gate contact connected to the diode doped region through the charge collector wire. However, Dyer discloses a configuration (Fig. 16) of a semiconductor integrated circuit device (200) with backside contacts (83) wherein there are both frontside S/D contacts (51) and frontside gate contacts (53) formed in the device. Dyer discloses that this configuration is a conventional configuration known in the art in these devices (col. 7 lines 45-53). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). Therefore absent evidence that the claimed configuration is significant, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Hung to include a frontside gate contact as it is a known feature in the described conventional devices.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210366846 (Hung et al) in view of US 20230069107 (Wei) and US 20220293597 (Hu et al) as applied to claim 10 above, and further in view of US 7816231 (Dyer et al).
As to claim 12, Hung in view of Wei and Hu disclose forming frontside contacts (208).
Hung in view of Wei and Hu does not disclose wherein the active semiconductor IC device further comprises a frontside gate contact connected to the diode doped region through the charge collector wire. However, Dyer discloses a configuration (Fig. 16) of a semiconductor integrated circuit device (200) with backside contacts (83) wherein there are both frontside S/D contacts (51) and frontside gate contacts (53) formed in the device. Dyer discloses that this configuration is a conventional configuration known in the art in these devices (col. 7 lines 45-53). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). Therefore absent evidence that the claimed configuration is significant, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Hung to include a frontside gate contact as it is a known feature in the described conventional devices.
Response to Arguments
Applicant’s arguments, see pages 6-9, filed 05/26/26, with respect to the rejection(s) of claim(s) 1, 10, and 19 under 102 and 103 respectively have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20230069107 (Wei).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 08/07/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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