DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species I (encompassing claims 1-9, 11-15, and 21-26) in the reply filed on 12/31/25 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 9/6/23. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the distance from the first crystalline semiconductor plug to the second crystalline semiconductor plug is less than a width of the semiconductor crystalline lateral portion (subject matter of claim 25) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 25 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 25 recites the distance from the first crystalline semiconductor plug to the second crystalline semiconductor plug is less than a width of the semiconductor crystalline lateral portion. As best as can be understood by the examiner, the distance from the first crystalline semiconductor plug (e.g., left 1141, Fig. 22A) to the second crystalline semiconductor plug (right 1141, Fig. 22A) is more than a width of the semiconductor crystalline lateral portion (114, Fig. 22A) (see also Examiner Annotated Fig. 22A below).
PNG
media_image1.png
664
724
media_image1.png
Greyscale
Examiner could not find written support in the Specification or the Drawings for the claimed limitation that the distance from the first crystalline semiconductor plug to the second crystalline semiconductor plug is less than a width of the semiconductor crystalline lateral portion. Examiner notes claim 25 was not originally presented and was submitted with the amendment filed 12/31/25.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25 recites the distance from the first crystalline semiconductor plug to the second crystalline semiconductor plug is less than a width of the semiconductor crystalline lateral portion. At least in the elected embodiment, the distance from the first crystalline semiconductor plug (e.g., left 1141, Fig. 22A) to the second crystalline semiconductor plug (right 1141, Fig. 22A) is more than a width of the semiconductor crystalline lateral portion (114, Fig. 22A) (see e.g., Examiner Annotated Fig. 22A above). As such, it is unclear to the examiner if the meaning of the limitation that “the distance from the first crystalline semiconductor plug to the second crystalline semiconductor plug is less than a width of the semiconductor crystalline lateral portion” is different than a plain meaning of the words in this phrase.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6, 21, 23, and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (U.S. 2021/0202475; “Hu”).
Regarding claim 1, Hu discloses a method comprising:
Forming a first transistor (104, Fig. 20) on a substrate (102, Fig. 20) (S11, Fig. 9) ([0021], [0074]);
Forming a first dielectric layer (120, Fig. 20) over the first transistor (S12, Fig. 9) ([0075]);
Forming a first trench (O3, Fig. 20) in the first dielectric layer (S13, Fig. 9) ([0076]), wherein a bottom of the first trench is at the substrate (102, Fig. 20) ([0094]);
Depositing an amorphous semiconductor layer in the first trench and over the first dielectric layer (S14, Fig. 9) ([0077]);
Crystallizing the amorphous semiconductor layer into a crystalline semiconductor layer (S15, Fig. 9) ([0078]); and
Forming a second transistor (170, Fig. 20) over the crystalline semiconductor layer (S16, Fig. 9) ([0079]).
Regarding claim 4, Hu discloses the second transistor has a channel material (SG2, Fig. 20) ([0053]-[0054]) different from a channel material of the first transistor ([0020], [0024]).
Regarding claim 6, Hu discloses the amorphous semiconductor layer is crystallized into the crystalline semiconductor layer by using a laser anneal ([0078], [0050]).
Regarding claim 21, Hu discloses a method comprising:
Forming a first transistor (104, Fig. 20) over a substrate (102, Fig. 20) (S11, Fig. 9) ([0021], [0074]);
Forming a first dielectric layer (120, Fig. 20) over the first transistor (S12, Fig. 9) ([0075]);
Forming a first crystalline semiconductor plug (142”, Fig. 20) extending through the first dielectric layer ([0077]-[0078]);
Forming a crystalline semiconductor lateral portion (SG2, Fig. 20) extending along a top surface of the first dielectric layer, wherein the crystalline semiconductor lateral portion is formed of a same material as the first crystalline semiconductor plug ([0078]); and
Forming a second transistor (170, Fig. 20) over the crystalline semiconductor lateral portion (S16, Fig. 9) ([0079]).
Regarding claim 23, Hu discloses the first crystalline semiconductor plug (142”, Fig. 20) is in contact with the substrate (102, Fig. 20) ([0074]).
Regarding claim 26, Hu discloses forming a second dielectric layer (190, Fig. 20) over the second transistor ([0071]); and forming metal vias (200, Fig. 20) in the second dielectric layer ([0071]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (U.S. 2021/0202475; “Hu”) as applied to claim 1 above, and further in view of Rachmady et al. (U.S. 2020/0212038 A1; “Rachmady”).
Regarding claim 5, Hu discloses forming a first transistor (104, Fig. 20) ([0021], [0074]) and forming a second transistor (170, Fig. 20) ([0021], [0079]). Yet, Hu does not disclose the transistors have different conductivity types. However, Rachmady discloses stacked transistors having different conductivity types ([0025]; Fig. 1). This has the advantage of forming a complementary field effect transistor (CMOS) device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Hu with the first transistor and the second transistors having different conductivity types, as taught by Rachmady, so as to form a CMOS device.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (U.S. 2021/0202475; “Hu”) as applied to claim 1 above, and further in view of Zhang et al. (U.S. 2017/0194151 A1; “Zhang”).
Regarding claim 7, Hu discloses the amorphous semiconductor layer is crystallized into the crystalline semiconductor layer by using a laser anneal ([0078], [0050]) but does not disclose the laser anneal is performed such that the amorphous semiconductor layer is turned into a liquid phase. However, Zhang discloses an crystallizing an amorphous semiconductor layer by using a liquid phase laser anneal ([0021]). This has the advantage of forming a high-quality crystalline semiconductor layer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Hu with the laser anneal performed such that the amorphous semiconductor layer is turned into a liquid phase, as taught by Zhang, so as to form a high-quality crystalline semiconductor layer.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (U.S. 2021/0202475; “Hu”) as applied to claim 1 above, and further in view of Ishizu et al. (U.S. 2022/0384433 A1; “Ishizu”).
Regarding claim 9, Hu discloses forming a second dielectric layer (190, Fig. 20) over the second transistor (170, Fig. 20) and forming a first via (200, Fig. 20) extending in the second dielectric layer to the second transistor ([0071]). Yet, Hu does not disclose forming a second via extending in the first dielectric layer and the second dielectric layer to the first transistor. However, Ishizu discloses forming a [second] via (358, Fig. 13B) extending in a first dielectric layer (336, Fig. 13B) and a second dielectric (356, Fig. 13B) to (as in “towards”) a first transistor ([0083]). This has the advantage of electrically connecting the first transistor and the second transistor. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Hu with a second via extending in the first dielectric layer and the second dielectric layer to the first transistor, as taught by Ishizu, so as to electrically connect the first transistor and the second transistor.
Allowable Subject Matter
Claims 11-15 are allowed.
Claim 11 contains allowable subject matter because of the limitation of performing an anneal process on the amorphous semiconductor material, the anneal process turning the amorphous semiconductor material into a crystalline semiconductor material; forming an epitaxial stack on the crystalline semiconductor material, the epitaxial stack comprising first semiconductor layers and second semiconductor layers alternating with the first semiconductor layers; and replacing the first semiconductor layers with a gate structure. Claims 12-15 depend on claim 11.
Claims 2-3, 8, 22, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/REEMA PATEL/Primary Examiner, Art Unit 2812
1/16/2026