Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election of species I, claims 1-16 in the reply filed on 1/5/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 17-20 are withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention.
Information Disclosure Statement
The information disclosure statements filed 9/6/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 9/6/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 10 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by CHOI
et al. (U.S. Patent Publication No. 2020/0312715).
Referring to figures 1-12, CHOI et al. teaches a semiconductor device, comprising:
a substrate (10);
one or more front pads (50/60) disposed on a front surface of the substrate (see figures 2, 2-6); and
a circuit layer (20, 30, 40, 45) comprising an insulating layer (20, 40) and at least one interconnection (30f) electrically connected to the one or more front pads (50/60), the insulating layer disposed between the one or more front pads (50/60) and the substrate (10), wherein a side surface of the circuit layer comprises a burr (550/650/750), the burr protruding a height that is below a level of a front surface of the circuit layer, or the burr forming a step portion in the circuit layer, or a combination thereof (see figures 6-7).
Regarding to claim 2, the circuit layer (20, 40, 45) comprises a first edge between the front surface of the circuit layer and the side surface of the circuit layer and a second edge formed by the burr, wherein the burr is more curved than the first edge (see figures 6-7).
Regarding to claim 3, wherein the burr has a gentler slope than a region in which the burr is not disposed on the side surface of the circuit layer (see figure 7).
Regarding to claim 4, the burr is disposed on a step portion on the side surface of the circuit layer or forms the step portion (see figure 7).
Regarding to claim 5, the step portion on the side surface of the circuit layer provides an additional front surface of the circuit layer, wherein the burr protrudes convexly from the additional front surface (see figure 7).
Regarding to claim 6, the burr comprises a mixed material, the mixed material comprising at least one of a material of the interconnection and a material of the substrate mixed with an insulating material of the insulating layer (see paragraph# 73).
Regarding to claim 7, the insulating material of the insulating layer comprises at least one of a silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof (see paragraph# 47).
Regarding to claim 10, a bonding insulating layer (90) disposed on the front surface of the circuit layer and surrounding the one or more front pads (50/60), wherein the burr is spaced apart from the bonding insulating layer (see figures 2-7).
Claim(s) 11-13, 15-16 is/are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by
KWEON et al. (U.S. Patent Publication No. 2023/0096678).
Referring to figures 1-14, KWEON et al. teaches a semiconductor package, comprising:
a plurality of semiconductor chips (CH, see figure 4a), wherein each of the semiconductor chips comprises:
a substrate (11);
one or more front pads (BP) disposed on a front surface of the substrate (11); and
a circuit layer (12/130) comprising an insulating layer (131) and at least one interconnection (132) electrically connected to the one or more front pads (122), the insulating layer disposed between the one or more front pads and the substrate, wherein one of the plurality of semiconductor chips further comprises a bonding insulating layer (121) disposed on a front surface of the circuit layer(110) and surrounding the one or more front pads, wherein the other of the plurality of semiconductor chips further comprise one or more rear pads (152) and bonding insulating layers (151), the one or more rear pads disposed on a rear surface of the substrate and the bonding insulating layers disposed on a rear surface of the substrate and surrounding the one or more rear pads (see figure 11), wherein the plurality of semiconductor chips (100/200) is bonded to each other through the bonding insulating layers (see figure 14), and wherein a side surface of the circuit layer of at least one of the plurality of semiconductor chips has a portion (12P), the portion protruding while being spaced apart from the bonding insulating layer, or the portion forming a step portion in the circuit layer, or a combination thereof (see figures 7b, 14).
Regarding to claim 12, the circuit layer (12/130) of at least one of the plurality of semiconductor chips comprises a first edge between the front surface of the circuit layer and the side surface of the circuit layer and a second edge protruding from the side surface of the circuit layer or forming a step portion, wherein the second edge is more curved than the first edge (see figure 7b).
Regarding to claim 13, the portion protruding from the side surface of the circuit layer or forming the step portion comprises a gentler slope than a remaining region of the side surface of the circuit layer (see figure 7b).
Regarding to claim 15, an encapsulant (260) encapsulating the plurality of semiconductor chips (100/200), wherein the portion protruding from the side surface of the circuit layer or forming the step portion is in contact with the encapsulant (see figures 7b, 14).
Regarding to claim 16, the substrate of at least one of the plurality of semiconductor chips comprises a recessed portion recessed between the substrate and the circuit layer (see figure 7b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI et al.
(U.S. Patent Publication No. 2020/0312715) as applied to claims 1-7, 10 above, and further in
view of KWEON et al. (U.S. Patent Publication No. 2023/0096678).
CHOI et al. teaches a semiconductor device, comprising: a substrate (10); one or more
front pads (50/60) disposed on a front surface of the substrate (see figures 2, 2-6); and a circuit layer (20, 30, 40, 45) comprising an insulating layer (20, 40) and at least one interconnection (30f) electrically connected to the one or more front pads (50/60), the insulating layer disposed between the one or more front pads (50/60) and the substrate (10), wherein a side surface of the circuit layer comprises a burr (550/650/750), the burr protruding a height that is below a level of a front surface of the circuit layer, or the burr forming a step portion in the circuit layer, or a combination thereof (see figures 6-7).
However, the reference does not clearly teach a density of the burr is lower than a density of the insulating layer (in claim 8) and the substrate comprises a recessed portion recessed between the substrate and the circuit layer (in claim 9).
KWEON et al. teaches a density of the burr (SiO) is lower than a density of the insulating layer (SiN, see paragraphs# 35, 28, meeting claim 8) and the substrate of at least one of the plurality of semiconductor chips comprises a recessed portion recessed between the substrate and the circuit layer (see figure 7b, meeting claim 9).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would a device having a density of the burr is lower than a density of the insulating layer and the substrate comprises a recessed portion recessed between the substrate and the circuit layer in CHOI et al. as taught by KWEON et al. because it is known in the art to improve the electrical properties and reliability of semiconductor package (see paragraph# 76).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWEON et al. (U.S. Patent Publication No. 2023/0096678) as applied to claims 11-13, 15-16 above, and further in CHOI et al. (U.S. Patent Publication No. 2020/0312715).
KWEON et al. teaches a semiconductor package, comprising:
a plurality of semiconductor chips (CH, see figure 4a), wherein each of the semiconductor chips comprises:
a substrate (11);
one or more front pads (BP) disposed on a front surface of the substrate (11); and
a circuit layer (12/130) comprising an insulating layer (131) and at least one interconnection (132) electrically connected to the one or more front pads (122), the insulating layer disposed between the one or more front pads and the substrate, wherein one of the plurality of semiconductor chips further comprises a bonding insulating layer (121) disposed on a front surface of the circuit layer(110) and surrounding the one or more front pads, wherein the other of the plurality of semiconductor chips further comprise one or more rear pads (152) and bonding insulating layers (151), the one or more rear pads disposed on a rear surface of the substrate and the bonding insulating layers disposed on a rear surface of the substrate and surrounding the one or more rear pads (see figure 11), wherein the plurality of semiconductor chips (100/200) is bonded to each other through the bonding insulating layers (see figure 14), and wherein a side surface of the circuit layer of at least one of the plurality of semiconductor chips has a portion (12P), the portion protruding while being spaced apart from the bonding insulating layer, or the portion forming a step portion in the circuit layer, or a combination thereof (see figures 7b, 14).
However, the reference does not clearly teach the portion protruding from the side surface of the circuit layer or forming the step portion comprises a mixed material, the mixed material comprising at least one of a material of the interconnection and a material of the substrate mixed with an insulating material of the insulating layer.
CHOI et al. teach the portion protruding from the side surface of the circuit layer or forming the step portion comprises a mixed material, the mixed material comprising at least one of a material of the interconnection and a material of the substrate mixed with an insulating material of the insulating layer (see paragraph# 73).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would a device having the portion protruding from the side surface of the circuit layer or forming the step portion comprises a mixed material, the mixed material comprising at least one of a material of the interconnection and a material of the substrate mixed with an insulating material of the insulating layer in KWEON et al. as taught by CHOI et al. because it is known in the art to improve performance of semiconductor package (see paragraph# 119).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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