Prosecution Insights
Last updated: July 17, 2026
Application No. 18/462,049

INTEGRATED CIRCUIT DEVICES INCLUDING VIA CAPACITORS

Non-Final OA §103
Filed
Sep 06, 2023
Priority
Sep 08, 2022 — RE 10-2022-0114461 +1 more
Examiner
CULLEN, PATRICK LAWRENCE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
13 granted / 16 resolved
+13.3% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
35 currently pending
Career history
72
Total Applications
across all art units

Statute-Specific Performance

§103
97.4%
+57.4% vs TC avg
§102
1.7%
-38.3% vs TC avg
§112
0.9%
-39.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 16 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Applicant is advised that should claims 3-5 be found allowable, claims 6-8 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Specifically, the only difference between claims 3-5 and 6-8 appears to be a simple rewording of the terms “active connection line” and “active wiring line” into the terms “pad connection line” and “pad wiring line” (emphasis added), respectively. It is interpreted that all pads can function as being “active”, while the term “active” itself is interpreted as referring to an intended use rather than a structural difference. Claim Rejections - 35 USC § 103 Claim(s) 1-2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Park (PGPub No. 20210375551). Regarding claim 1, Park in combination with Collins teaches an integrated circuit device comprising: a dielectric layer; a first power delivery network layer on a first surface of the dielectric layer; a second power delivery network layer on a second surface of the dielectric layer, wherein the second surface of the dielectric layer is opposite to the first surface of the dielectric layer in a vertical direction; and a via capacitor between the first surface and the second surface of the dielectric layer, wherein the via capacitor includes a first via electrode structure and a second via electrode structure that are spaced apart from each other in one of a first horizontal direction and a second horizontal direction that intersects with the first horizontal direction, and a first end portion and a second end portion that is opposite to the first end portion of the via capacitor are electrically connected to the first power delivery network layer and the second power delivery network layer, respectively (Fig. 2J points to an IC structure comprising a support structure 202 (dielectric layer), interconnects 252 (first power delivery network layer), and TSVs 242-1 (first via electrode structure) and 242-2 (second via electrode structure). [0046] further points to the thinning of back side 262-1 such that an electrical connection (second power delivery network layer) may be made thereto.). Regarding claim 2, Park teaches wherein the first via electrode structure includes a first via electrode between the first surface and the second surface of the dielectric layer and a first via insulating layer on opposing sidewalls of the first via electrode, and wherein the second via electrode structure includes a second via electrode between the first surface and the second surface of the dielectric layer and a second via insulating layer on opposing sidewalls of the second via electrode (Fig. 2J points to TSVs 242-1 (first via electrode structure) and 242-2 (second via electrode structure) each comprising an electrically conductive material 208 (first via electrode; second via electrode) and a dielectric material 206 (first via insulating layer; second via insulating layer).). Regarding claim 9, Park teaches wherein the dielectric layer includes an insulating material and/or a semiconductor material ([0031] points to the support structure 202 (dielectric layer) being composed of any material that may serve as a foundation upon which an IC may be built, such as a semiconductor substrate composed of semiconductor material.). Claim(s) 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Park in further view of Park2 (US Patent No. 9691684). Regarding claim 3, Park2 teaches wherein at least one of the first power delivery network layer and the second power delivery network layer includes a first active connection line that is electrically connected to one of the first via electrode structure and the second via electrode structure and a first active wiring line that is electrically connected to the first active connection line (Figs. 1-2 point to a first wiring structure 92.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Park and Park2, such that a connection line and wiring line are formed and electrically connected to at least one of the via electrode structures in order to establish a vertical electrical connection through the device. Regarding claim 4, Park2 teaches wherein the first active wiring line extends in the first horizontal direction on one of the first surface and the second surface of the dielectric layer, and the first active connection line extends in the second horizontal direction on the one of the first surface and the second surface of the dielectric layer (Figs. 1-2 point to a first wiring structure 92.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park and Park2, such that the wiring line and connection line are along the first and second horizontal directions, respectively, in order to establish a vertical electrical connection that maintains adequate contact with a via electrode structure and/or fits within the critical dimensions of the overall structure. Regarding claim 5, Park2 teaches wherein the first active wiring line extends in the second horizontal direction on one of the first surface and the second surface of the dielectric layer, and the first active connection line extends in the first horizontal direction on the one of the first surface and the second surface of the dielectric layer (Figs. 1-2 point to a second wiring structure 94.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park and Park2, such that the wiring line and connection line are along the second and first horizontal directions, respectively, in order to establish a vertical electrical connection that maintains adequate contact with a via electrode structure and/or fits within the critical dimensions of the overall structure. Regarding claim 6, Park2 teaches wherein at least one of the first power delivery network layer and the second power delivery network layer includes a first pad connection line that is electrically connected to one of the first via electrode structure and the second via electrode structure and a first pad wiring line that is electrically connected to the first pad connection line (Figs. 1-2 point to a first wiring structure 92.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park and Park2, such that a connection line and wiring line are formed and electrically connected to at least one of the via electrode structures in order to establish a vertical electrical connection through the device. Regarding claim 7, Park2 teaches wherein the first pad wiring line extends in the first horizontal direction on one of the first surface and the second surface of the dielectric layer, and the first pad connection line extends in the second horizontal direction on the one of the first surface and the second surface of the dielectric layer (Figs. 1-2 point to a first wiring structure 92.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park and Park2, such that the wiring line and connection line are along the first and second horizontal directions, respectively, in order to establish a vertical electrical connection that maintains adequate contact with a via electrode structure and/or fits within the critical dimensions of the overall structure. Regarding claim 8, Park2 teaches wherein the first pad wiring line extends in the second horizontal direction on one of the first surface and the second surface of the dielectric layer, and the first pad connection line extends in the first horizontal direction on the one of the first surface and the second surface of the dielectric layer (Figs. 1-2 point to a second wiring structure 94.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park and Park2, such that the wiring line and connection line are along the second and first horizontal directions, respectively, in order to establish a vertical electrical connection that maintains adequate contact with a via electrode structure and/or fits within the critical dimensions of the overall structure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 06, 2023
Application Filed
May 01, 2026
Non-Final Rejection mailed — §103
Jun 04, 2026
Examiner Interview Summary
Jun 04, 2026
Applicant Interview (Telephonic)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+33.3%)
3y 5m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 16 resolved cases by this examiner. Grant probability derived from career allowance rate.

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