Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed January 13, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 11, 17, 19
b. Pending: 1-21
Claims 1, 4, 7, 11, 12, 13, 17, and 19 have been amended and claim 21 is new.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 1 and 4 are objected to because of the following informality:
The amendments of both claims 1 and 4 were not indicated appropriately using strike-through, underline, etc. In other words, the strike-throughs and underlining were not consistent with whether the content was original or amended.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 11-12, 17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Nakano et al. (US Pub. US 20120069626 A1; “Nakano”) in view of Ooishi et al. (US Pub. 20030169622 A1; “Ooishi”).
Regarding independent claim 1, Nakano discloses a semiconductor device
(Fig. 1: semiconductor memory device; [0103]; also see Fig. 10: semiconductor
memory device; [0138]) comprising:
a current direction control circuit (22a & 22b) configured to selectively provide a first bias voltage and a second bias voltage to a row voltage line and a column voltage line ([0139]: a reforming voltage pulse from the reforming voltage application circuit 22b is applied to a bit line or a word line in which the number of times of error correction exceeds a predetermined value; also [0016]: a predetermined bias voltage is applied to a selected word line and a selected bit line respectively), based on the current direction control signal ([0130] & [0133]; [0150]);
a row decoder (word line decoder 17; [0103]) configured to select at least one word line, among a plurality of word lines ([0104]: as shown in FIG. 2, the memory cell array 15a is configured to have m.times.n memory cells 14a arranged at cross points of m bit lines (corresponding to column selection lines) BL1 to BLm that extend in a column direction and n word lines (corresponding to row selection lines) WL1 to WLn that extend in a row direction; also [0126]: it is also possible to simultaneously perform reforming to a plurality of memory cells connected to selected bit lines by simultaneously selecting a plurality of word lines), based on the row address signal ([0022]: The control circuit 20 controls the word line decoder 17, the bit line decoder 16, a voltage application circuit 22 based on an address signal inputted from the address line 18, a data input signal (during programming) inputted from the data line 19, and a control input signal inputted from the control signal line 21 to perform each operation of reading, programming, and erasing of the memory cell array 15a) and configured to drive the selected word line to a voltage level of the row voltage line (per [0022], the control circuit controls the voltage application circuits 22; per [0023]: The voltage application circuit 22 switches, corresponding to an operation mode, each voltage of a word line, a bit line, and a source line that are necessary to read, program, and erase in the memory cell array 15a, and supplies the switched voltage to the memory cell array 15a);
a column decoder (bit line decoder 16; [0103]) configured to select at least one bit line, among a plurality of bit lines ([0104]; also [0108]: a selected memory cell connected to one or a plurality of bit lines), based on the column address signal ([0022]) and configured to drive the selected bit line to a voltage level of the column voltage line ([0022] & [0023]);
a memory cell array (Fig. 2: memory cell array 15a; [0104]) comprising a plurality of memory cells that are disposed at intersecting locations of the plurality of word lines and the plurality of bit lines ([0104]); and
a data output circuit (Fig. 10: reading circuit 23 and ECC (Error-Correcting Code) circuit 24; [0139]-[0140]) configured to detect data that has been stored in selected memory cells ([0110]: The reading circuit 23 determines a resistance state of a variable resistance element of a memory cell to be read specified by a selected bit line and a selected word line), among the plurality of memory cells ([0104]), after a start of a read operation and configured to detect, correct ([0142]: the ECC circuit 24 determines whether a current voltage characteristic of a variable resistance element of a memory cell is within the first set range, based on presence of a data error, and corrects the data when there is a data error; [0140]: The ECC circuit 24 can be separately provided instead of being built in the control circuit 20), and output ([0023]: Data is read from the memory cell array 15a via the bit line decoder 16 and a reading circuit 23. The reading circuit 23 determines a data state, transfers the determination result to the control circuit 20, and outputs the result to the data line 19) an error of the detected data ([0151]: the control circuit 20 reads the resistance state stored in the variable resistance element of the selected memory cell (step S70), and determines whether the data of the selected memory cell is correctly written (step S71). Examiner concludes that the resistance state helps determine whether data is correct or erroneous, therefore the output of the reading circuit 23 may include outputting error information).
Nakano does not disclose:
a control circuit configured to generate a current direction control signal, a row address signal, and a column address signal based on a command signal, an address signal, and a data signal during write and read operations, and to generate the current direction control signal, the row address signal, and the column address signal, based on an error correction code (ECC) information signal in a re-write operation;
However, Ooishi teaches:
a control circuit (Fig. 1: control circuit 5; [0098]) configured to generate a current direction control signal ([0097]: control circuit 5 for adjusting a current quantity of comparison reference current Iref generated by reference current generating circuit 2), a row address signal, and a column address signal based on a command signal, an address signal, and a data signal during write and read operations ([0187]: In FIG. 10, control circuit 5 includes…an address registration control section 12 for controlling registration of an address of a memory cell according to a non-coincidence detection indicating signal from non-coincidence detecting section 15 and output data of sense amplifier 4; and address storage sections 17 and 18 storing an address signal AD under control of the address registration control section 16. Address storage section 17 stores the address of a memory cell address having a risen threshold voltage, and address storage section 18 stores the address of a memory cell having a fallen threshold voltage. Examiner asserts that writing and reading is required to determine the address of the memory cell with the fallen threshold voltage), and to generate the current direction control signal, the row address signal, and the column address signal, based on an error correction code (ECC) information signal ([0220]: In data reading, when a margin failure is further detected at a registered address, a prescribed error processing is performed. In FIG. 12, there is shown a configuration in which a quantity of reference current is adjusted according to output signals of coincidence detecting circuits 21 and 23, and the address of a memory cell causing a margin failure once is not re-registered) in a re-write operation ([0189]: a sufficient margin can be secured in rewriting, by adjusting the reference current in detection of a margin failure);
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Ooishi to Nakano wherein a semiconductor device comprises a control circuit configured to generate a current direction control signal, a row address signal, and a column address signal based on a command signal, an address signal, and a data signal during write and read operations, and to generate the current direction control signal, the row address signal, and the column address signal, based on an error correction code (ECC) information signal in a re-write operation in order to correctly read data from a memory cell, even if it has deteriorated, by modifying the reference current based on characteristics of the cell (Ooishi, [0110]).
Regarding claim 3, Nakano and Ooishi together disclose the limitations of claim 1. Nakano further discloses:
the data output circuit comprises an ECC circuit (Fig. 10: reading circuit 23 and ECC (Error-Correcting Code) circuit 24) configured to detect and correct the error of the data ([0142]); and
the ECC circuit (23 & 24) generates the ECC information signal ([0140]), the ECC information signal indicating a number of corrected data after the start of the read operation ([0057]: the error counter stores the number of times of error correction performed by the ECC circuit, in reading information stored in the memory cell related to the error counter in the memory cell array), locations of memory cells that have output the corrected data ([0057]: when a value of the error counter reaches a predetermined second set value, the reforming voltage application circuit applies the reforming voltage pulse to the memory cell related to the error counter, via the memory cell selecting circuit), and a type of error of the corrected data ([0142]: the current voltage characteristic being outside a first set range means that data to be programmed is not programmed, or that data to be erased is not erased. In the present embodiment, the ECC circuit 24 determines whether a current voltage characteristic of a variable resistance element of a memory cell is within the first set range, based on presence of a data error, and corrects the data when there is a data error. Examiner concludes that the ECC circuit 24 determines whether the type of error is related to programming or erasing data).
Regarding claim 4, Nakano and Ooishi together disclose the limitations of claim 3. Nakano does not disclose
wherein the control circuit controls the re-write operation, and when the number of the corrected data is greater than a set number, the control circuit generates the row address signal and the column address signal corresponding to the locations of the memory cells that have output the corrected data in the re-write operation, and wherein the control circuit generates the current direction control signal based on the type of error of the corrected data.
However, Ooishi teaches:
wherein the control circuit (Fig. 1: 5) controls the re-write operation ([0189]), and when the number of the corrected data is greater than a set number, the control circuit generates the row address signal and the column address signal corresponding to the locations of the memory cells that have output the corrected data in the re-write operation ([0221]: When the number of times of margin failures does not reach the maximum allowable number, the number of detected margin failures of the registered address is incremented by one and a quantity of reference current is adjusted according to a number of detected margin failures; [0132]: Detection of a margin failure is performed on the basis of coincidence/non-coincidence between logical levels of output signals of sense amplifiers 3 and 4. Examiner asserts that “registered address” indicates the row and column of a specific memory cell), and
wherein the control circuit generates the current direction control signal based on the type of error of the corrected data ([0099]: a magnitude of comparison reference current Iref generated by reference current generating circuit 2 is adjusted according to the direction in which a threshold voltage varies due to the change in characteristic. Thus, there can be generated a reference current adapted to a threshold voltage characteristic of each selected memory cell… Here, the term "threshold voltage characteristic" indicates a variation (shift) in threshold voltage for data at the same logical level).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of modified Ooishi to Nakano wherein the control circuit controls the re-write operation, and when the number of the corrected data is greater than a set number, the control circuit generates the row address signal and the column address signal corresponding to the locations of the memory cells that have output the corrected data in the re-write operation, and wherein the control circuit generates the current direction control signal based on the type of error of the corrected data in order to correctly read data from a memory cell, even if it has deteriorated, by modifying the reference current based on characteristics of the cell (Ooishi, [0110]).
Regarding independent claim 11, Nakano discloses a semiconductor device (Fig. 1: semiconductor memory device; also see Fig. 10: semiconductor memory device) comprising:
a current direction control circuit (22a & 22b) configured to selectively provide a first bias voltage and a second bias voltage to a row voltage line and a column voltage line ([0139]; [0016]), based on the current direction control signal ([0130] & [0133]);
a row decoder (17; [0103]) configured to select at least one word line, among a plurality of word lines ([0104]; [0126]), based on the row address signal ([0022]) and configured to drive the selected word line to a voltage level of the row voltage line ([0022]; [0023]);
a column decoder (16) configured to select at least one bit line, among a plurality of bit lines ([0104]; [0108]), based on the column address signal ([0022]) and configured to drive the selected bit line to a voltage level of the column voltage line ([0022] & [0023]); and
an ECC circuit (Fig. 10: 23 & 24) configured to detect and correct an error of data ([0142]) that is output after the start of the read operation, and configured to generate an ECC information signal indicating a number of corrected data ([0057]), locations of memory cells ([0021]) that have output the corrected data ([0140]; [0142]; [0151]), and a type of error of the corrected data ([0142]).
Nakano does not disclose:
a control circuit configured to control a re-write operation and generate a current direction control signal, a row address signal, and a column address signal based on an error correction code (ECC) information signal in the re-write operation, after a start of a read operation or whenever a set time interval elapses;
However, Ooishi teaches:
a control circuit (Fig. 1: 5) configured to control a re-write operation (per Fig. 1, the control circuit 5 controls the reference current generating circuit 2, which is required to adjust the reference current during re-write; [0189]) and generate a current direction control signal, a row address signal, and a column address signal based on an error correction code (ECC) information signal in the re-write operation, after a start of a read operation ([0214]: At the start of reading, a generated memory cell address is applied to reference current generating sections 20 and 22 of control circuit 5 and is compared with programmed addresses therein; [0220]) or whenever a set time interval elapses;
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ooishi to modified Nakano wherein a semiconductor device comprises a control circuit configured to control a re-write operation and generate a current direction control signal, a row address signal, and a column address signal based on an error correction code (ECC) information signal in the re-write operation, after a start of a read operation or whenever a set time interval elapses in order to correctly read data from a memory cell, even if it has deteriorated, by modifying the reference current based on characteristics of the cell (Ooishi, [0110]).
Regarding claim 12, Nakano and Ooishi together disclose the limitations of claim 11. Nakano further discloses:
wherein the control circuit (Fig. 1: 20) generates the current direction control signal ([0133] & [0130]; [0150]) based on the type of error of the corrected data ([0142]).
Nakano does not disclose:
wherein when it is determined that the number of the corrected data is greater than a set number based on the ECC information signal after the start of the read operation, the control circuit generates the row address signal and the column address signal corresponding to the locations of the memory cells that have output the corrected data in the re-write operation, and
However, Ooishi teaches:
wherein when it is determined that the number of the corrected data is greater than a set number based on the ECC information signal after the start of the read operation ([0214]; [0220]), the control circuit generates the row address signal and the column address signal corresponding to the locations of the memory cells that have output the corrected data in the re-write operation ([0221]; [0132]), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ooishi to modified Nakano wherein when it is determined that the number of the corrected data is greater than a set number based on the ECC information signal after the start of the read operation, the control circuit generates the row address signal and the column address signal corresponding to the locations of the memory cells that have output the corrected data in the re-write operation in order to correctly read data from a memory cell, even if it has deteriorated, by modifying the reference current based on characteristics of the cell (Ooishi, [0110]).
Regarding independent claim 17, Nakano discloses an operating method (Fig. 12; [0147]) of a semiconductor device (Fig. 10: semiconductor memory device), comprising:
a read operation of outputting data stored in a selected memory cell (Fig. 12: step S70; [0151]: the control circuit 20 reads the resistance state stored in the variable resistance element of the selected memory cell (step S70);
an operation of receiving error correction code (ECC) information from an ECC circuit (step S60; [0147]: the control circuit 20 first reads the number of times of data correction of the selected bit line held in the error counter 31) that detects and corrects an error of the data ([0142]) after a start of a read operation ([0057]: the error counter stores the number of times of error correction performed by the ECC circuit, in reading information stored in the memory cell related to the error counter in the memory cell array, and when a value of the error counter reaches a predetermined second set value, the reforming voltage application circuit applies the reforming voltage pulse to the memory cell related to the error counter);
an operation of determining whether a number of corrected data ([0057]) is greater than a set number ([0139]; [0153]) based on the ECC information ([0057]);
an operation of providing a current having a direction ([0133] & [0130]; [0150]. Examiner concludes that the control signal from the control circuit 20 to the reforming voltage application circuit 22b or the write voltage application circuit 22a, which the Examiner has identified as the current direction control signal, has a direction because in Figs. 1 and 10, the arrows between control circuit 20 and both the reforming voltage application circuit 22b and the write voltage application circuit 22a are bidirectional) based on the type of error to the memory cells that have output the corrected data ([0142]).
Nakano does not disclose:
an operation of performing a re-write operation when the number of corrected data is greater than the set number, wherein the re-write operation comprises an operation of identifying locations of memory cells that have output the corrected data and a type of error of the corrected data based on the ECC information; and
However, Ooishi teaches:
an operation of performing a re-write operation ([0189]) when the number of corrected data is greater than the set number, wherein the re-write operation comprises an operation of identifying locations of memory cells that have output the corrected data ([0221]) and a type of error of the corrected data based on the ECC information ([0099]); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ooishi to modified Nakano wherein the operating method comprises an operation of performing a re-write operation when the number of corrected data is greater than the set number, wherein the re-write operation comprises an operation of identifying locations of memory cells that have output the corrected data and a type of error of the corrected data based on the ECC information in order to correctly read data from a memory cell, even if it has deteriorated, by modifying the reference current based on characteristics of the cell (Ooishi, [0110]).
Regarding claim 21, Nakano and Ooishi together disclose the limitations of claim 3. Claim 21 is mostly the same as the second limitation of claim 4, and henceforth is rejected for the same reasons.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nakano (US Pub. 20120069626 A1) and Ooishi (US Pub. 20030169622 A1) as applied to claims 1 and 11 above, and further in view of Liu (CN 114944181 A).
Regarding claim 2, Nakano and Ooishi together disclose the limitations of claim 1. Per claim 1, Nakano discloses a current direction control circuit and selecting the row voltage line and the column voltage line to which the bias voltages are provided.
Neither Nakano nor Ooishi discloses:
wherein the current direction control circuit selects the row voltage line and the column voltage line to which the first bias voltage and the second bias voltage are provided, based on the current direction control signal, so that voltages having different polarities are provided to the row voltage line and the column voltage line.
However, Liu teaches:
wherein the current direction control circuit selects the row voltage line and the column voltage line to which the first bias voltage ([n0006]: first voltage) and the second bias voltage ([n0006]: second voltage) are provided, based on the current direction control signal, so that voltages having different polarities ([n0012]: the first voltage is a positive voltage; and the second voltage is a negative voltage) are provided to the row voltage line and the column voltage line ([n0027]: the operation method includes: applying a first voltage to a selected word line coupled to a selected phase change memory cell, and applying a second voltage to a selected bit line coupled to the selected phase change memory cell).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Liu to modified Nakano wherein the current direction control circuit selects the row voltage line and the column voltage line to which the first bias voltage and the second bias voltage are provided, based on the current direction control signal, so that voltages having different polarities are provided to the row voltage line and the column voltage line in order to reduce damage to phase change memory cells by stepping up the voltage applied to the word lines gradually (Liu, [n0003]).
Regarding claim 14, Nakano and Ooishi together disclose all the limitations of claim 11. Claim 14 contains a second limitation that is the same in claimed subject matter to claim 2 and so the second limitation is rejected for the same reasons as claim 2. Further through Nakano:
the type of error comprises a set error and a reset error ([0024]: the variable resistance element is based on a phenomenon that the variable resistance element becomes a low resistance state or a high resistance state; [0141]: a range of a resistance value from 1 K.OMEGA., to 10 k.OMEGA. can be the first set range in a low resistance state, and a range of a resistance value from 20 k.OMEGA., to 1 M.OMEGA. can be the first set range in a high resistance state; [0142]: the current voltage characteristic being outside a first set range means that data to be programmed is not programmed, or that data to be erased is not erased. In the present embodiment, the ECC circuit 24 determines whether a current voltage characteristic of a variable resistance element of a memory cell is within the first set range, based on presence of a data error, and corrects the data when there is a data error. Examiner concludes that the high and low resistance states may indicate data errors. Examiner notes that per the Summary section of the Specification of the present application, the reset state is analogous to a high resistance state [0037] and the set state is analogous to a low resistance state [0044]), the set error indicative of the corrected data having a set state ([0157]: The control circuit 20 applies the reforming voltage pulse from the reforming voltage application circuit 22b when the amount of current detected by the reading circuit 23 is outside the second set range; also see [0061]), the reset error indicative of the corrected data having a reset state ([0142]);
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Nakano (US Pub. 20120069626 A1) and Ooishi (US Pub. 20030169622 A1) as applied to claims 3 and 11 above, and further in view of Ong (US Pub. 20160284422 A9).
Regarding claim 7, Nakano and Ooishi together disclose the limitations of claim 3, and further through Nakano:
wherein the control circuit (Fig. 1: 20) generates the current direction control signal ([0133] & [0130]; [0150]) based on the type of error of the corrected data ([0142]).
Neither Nakano nor Ooishi disclose:
further comprising a timer configured to generate an interval information signal whenever a set time interval elapses,
wherein the control circuit controls the re-write operation, and when the control circuit receives the interval information signal, the control circuit generates the row address signal and the column address signal corresponding to locations of memory cells that have output the corrected data based on the ECC information signal in the re-write operation, and
However, Ong teaches:
further comprising a timer configured to generate an interval information signal whenever a set time interval elapses ([0029]: Based on failure modes and stress level (voltage, current, temperature, etc) statistical data, the smart memory can be automatically configured to provide a certain fix refresh interval. The refresh interval can be 3 seconds, 10 days, 5 weeks, 2 months, or more, for example. The time can be determined by an internal very low power clock),
wherein the control circuit controls the re-write operation ([0029]), and when the control circuit receives the interval information signal, the control circuit generates the row address signal and the column address signal corresponding to locations of memory cells that have output the corrected data based on the ECC information signal in the re-write operation ([0029]: Refresh cycle consists of reading the entire memory and then re-writing the same data. The circuitry can…implement the read and re-write function similar to the write-verify re-write circuitry; [0132]: A re-write operation will now be explained in greater detail. Depending on the memory system specification, the tagged address from the defective write operation can be used to re-write the memory cell located at the tagged address), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ong to modified Nakano wherein the device further comprises a timer configured to generate an interval information signal whenever a set time interval elapses, and wherein the control circuit controls the re-write operation, and when the control circuit receives the interval information signal, the control circuit generates the row address signal and the column address signal corresponding to locations of memory cells that have output the corrected data based on the ECC information signal in the re-write operation in order to improve system performance by using a System-in-Package device with good connectivity between memory arrays and processor chips (Ong, [0171]).
Regarding claim 13, Nakano and Ooishi together disclose the limitations of claim 11. Claim 13 recites mostly the same limitations as claim 7, and henceforth is rejected for the same reasons.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano (US Pub. 20120069626 A1) in view of Ooishi (US Pub. 20030169622 A1) and Ong (US Pub. 20160284422 A9).
Independent claim 19 contains a first limitation that has subject matter that combines the first two limitations of claim 7, a second limitation that is mostly the same as part of the fourth limitation of claim 17, and a third limitation that is a combination of the fourth and fifth limitations of claim 17. Thus, claim 19 is rejected for the same reasons.
Allowable Subject Matter
Claims 5-6, 8-10, 15-16, 18, and 20 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claims and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824
3/21/2026
/PHO M LUU/Primary Examiner, Art Unit 2824