Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 1/6/26 is acknowledged. The traversal is on the ground(s) that no serious burden exists in examination of both inventions. This is not found persuasive because different classification for the two claimed inventions is proof of serious burden in and of itself. As stated in MPEP 808.02, a serious burden is present when there is A) Separate classification thereof: this shows that each invention has attained recognition in the art as a separate subject for inventive effort, and also a separate field of search. Patents need not be cited to show separate classification. The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 9, 11, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McCollum US 7224042.
Pertaining to claim 1, McCollum teaches a semiconductor chip comprising:
a front end of line (FEOL) 16/18 including an active layer N+ region see Figure 2B marked up below;
a back end of line (BEOL) 12/40 including a plurality of metal layers see Figure 2B including a wire 20B/44B;
an optional dicing line 26 along which dicing is optionally performed;
an isolation block 54/58 configured to process a signal for a discontinuous wire when the wire is discontinuous by being diced along the optional dicing line 26; and
a chip die on which the active layer is not formed around a cross section cut by the optional dicing line. See Figure 2B marked up below
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392
582
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Pertaining to claim 2, McCollum teaches the semiconductor chip of claim 1, wherein the chip die comprises one or more of a central processing unit (CPU) core, a graphics processing unit (GPU core, an neural processing unit (NPU core, and a memory block. McCollum teaches memory Col 4 lines 40-48
Pertaining to claim 3, McCollum teaches the semiconductor chip of claim 1, wherein a number of the plurality of metal layers located around a cross-section of the optional dicing line is equal to or less than a number of the plurality of metal layers in a place other than a region around the cross-section of the optional dicing line. See Figure 2B marked up below
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362
532
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Pertaining to claim 4, McCollum teaches the semiconductor chip of claim 3, wherein a signal layer, which is one layer among the plurality of metal layers around the cross-section of the optional dicing line, is composed of a wire. See Figure 2B marked up below
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322
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Pertaining to claim 5, McCollum teaches the semiconductor chip of claim 1, wherein at least a portion of the wire is exposed on a cross-section of the optional dicing line. Wires 20B/44B ends will be exposed when separated at the scribe line as taught by McCollum Col 1 lines 48-67, or, they are “exposed to the scribe line” as shown in Figure 2B
Pertaining to claim 7, McCollum teaches the semiconductor chip of claim 1, wherein each semiconductor chip obtained by dicing along the optional dicing line is configured to function as a single chipset, and each semiconductor chip not diced along the optional dicing line is configured to function as a single chipset. McCollum teaches two separate circuits 60 and 62, they function as “a single chipset”
Pertaining to claim 9, McCollum teaches a semiconductor chip comprising:
an active layer N+ regions see Figure 2B;
a semiconductor wiring layer including a wire 20B/44B;
an optional dicing line 26 along which dicing is optionally performed;
an isolation block 54/58 configured to process a signal for a discontinuous wire when the wire is discontinuous by being diced along the optional dicing line; and
a chip die on which the active layer is not formed around a cross section cut by the optional dicing line see Figure 2B marked up below.
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392
582
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Pertaining to claim 11, McCollum teaches the semiconductor chip of claim 9, wherein a number of the semiconductor wiring layers around a cross-section of the optional dicing line is equal to or less than a number of semiconductor wiring layers located in a place other than a region around the cross-section of the optional dicing line. See rejection of claim 3 above, metal layers = wiring layers
Pertaining to claim 13, McCollum teaches the semiconductor chip of claim 9, wherein the isolation block is configured to perform a function of preventing an electric signal for the discontinuous wire from floating, shorting, and leaking. McCollum teaches shorting prevention of this configuration Col 3 lines 9-20
Allowable Subject Matter
Claims 6, 8, 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not teach or suggest pertaining to claim 6 a chip further comprising a molding member configured to surround the chip die, wherein the wire exposed on the cross-section of the optional dicing line is in direct contact with the molding member
The prior art does not teach or suggest pertaining to claim 8 wherein the chip die has two optional dicing lines, and at least one of the two optional dicing lines is diced to form a plurality of types of chip dies, or the two optional dicing lines are not diced to form a single type of chip die
The prior art does not teach or suggest pertaining to claim 10 wherein the isolation block includes a one time programmable (OTP) memory configured to activate the isolation block, when the chip die is diced along the optional dicing line.
The prior art does not teach or suggest pertaining to claim 12 wherein the isolation block is activated through an external pin or an external memory
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817