DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawing received on 02/03/2026 is acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leeser et al., US 2020/0244244 in view of Nguyen et al., US 2018/0047544.
With respect to independent claim 1, Leeser et al. shows the invention substantially as claimed including an apparatus 100 for processing substrates 109, the apparatus comprising: a process chamber including a plurality of processing spaces 101 in which the substrates are simultaneously processed using plasma; a substrate supporter 107 provided to each of the processing spaces, the substrate supporter including a plurality of stages configured to support the substrates; and an impedance matcher 137 provided to the process chamber, (see, for example, Figs. 2, 3B, 4B-6, and their descriptions, especially paragraphs 0006, 0020, 0022-0023, 0027, 0029-0030, 0033, 0036-0037, 0043-0045, 0050, 0054, 0056-0058, Figs. 2 and 3B are shown below).
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With respect to the impedance matcher detecting impedances under the plurality of stages while simultaneously processing the substrates, comparing the detected impedances with a reference impedance to calculate impedance compensation values by the plurality of stages, and matching the impedances of the plurality of stages based on the impedance compensation values, it should be noted that such limitations are directed to method limitations instead of apparatus limitations, and since an apparatus is being claimed as the instant invention, the method teachings are not considered to be the matter at hand, since a variety of methods can be done with the apparatus. The method limitations are viewed as intended uses which do not further limit, and therefore do not patentably distinguish the claimed invention. The impedance matcher of the apparatus of Leeser et al. is capable of performing the claimed limitations if the method to be performed within the apparatus requires it. Additionally, it should be noted that Leeser et al. clearly discloses that the electrode 105 can be the bottom electrode (see, for example, paragraph 0022); the substrate supports comprise a sensor module measuring voltages and current (see, for example, paragraph 0023); the matching module 137 is configured to control impedance matching within the system 100, wherein the matching module 137 is a network of capacitors and inductors that can be adjusted to tune impedance within the various plurality of processing spaces 101 by establishing a closed-loop feedback monitoring and control network (see, for example, paragraph 0030); having a reference impedance and using the balancing capacitors to match the real component of impedance when there is a difference of the real component of impedance between the processing spaces (see, for example, paragraphs 0037, 0050, 0054, and 0056). Therefore, Leeser et al. discloses that the apparatus performs the claimed limitations. This notwithstanding, a prima facie case of obviousness still exists because it would have been obvious to one of ordinary skill in the art to optimize the impedance between the plurality of spaces during routine experimentation depending upon, for example, the desired plasma uniformity, plasma characteristics, and plasma density, and such limitations would not lend patentability to the instant application absent the showing of unexpected results.
Leeser et al. does not expressly disclose that the impedance matcher selects any one of the stages as a master stage and the impedance matcher sets an impedance of the master stage as the reference impedance. Nguyen et al. discloses an apparatus for processing substrates having a plurality of processing spaces and plurality of impedance circuits that are configured in a master-slave relationship (see, for example, Fig. 1 and its description, especially paragraph 0019, Fig. 1 is shown below).
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Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the impedance matcher of the apparatus of Leeser et al., so that the plurality of impedance circuits are configured in a master-slave relationship because such configuration is known and used in the art as a suitable configuration to effectively and efficiently control the shape of the plasma within the process regions as desired/needed.
With respect to the master stage having a maximum RF current value among RF current values of the plurality of stages that are measured while transmitting RF power that generates the plasma through a ground path of the plurality of stages while the substrates are simultaneously processed, it should be noted that such limitation is directed to a method limitation instead of an apparatus limitation, and since an apparatus is being claimed as the instant invention, the method teachings are not considered to be the matter at hand, since a variety of methods can be done with the apparatus. The method limitations are viewed as intended uses which do not further limit, and therefore do not patentably distinguish the claimed invention. The impedance matcher of the apparatus of Leeser et al. modified by Nguyen et al. is capable of performing the claimed limitation if the method to be performed within the apparatus requires it. Additionally, a prima facie case of obviousness still exists because it would have been obvious to one of ordinary skill in the art before the invention was filed to use a substrate support having a desired current value as the master substrate support, depending upon, for example, the desired plasma uniformity, characteristics, and/or density, and such limitation would not lend patentability to the instant application absent the showing of unexpected results.
With respect to claim 2, as stated above, Leeser et al. discloses that the substrate supports comprise a sensor module measuring voltages and current (see, for example, paragraph 0023), a closed-loop feedback monitoring and control network for tuning the impedance within the various plurality of processing spaces (see, for example, paragraphs 0030), having a reference impedance and using the balancing variable capacitors to match the real component of impedance when there is a difference of the real component of impedance between the processing spaces which is performed by calculating a compensating value to adjust/control one or more of the variable capacitor (see, for example, paragraphs 0037, 0050, 0054, and 0056). With respect to the voltages and current being measured in real time during the substrate being simultaneously process, and calculating the impedance compensation values based on the impedances by the stages from the sensor module, it should be noted that such limitation is directed to a method limitation instead of an apparatus limitation, and since an apparatus is being claimed as the instant invention, the method teachings are not considered to be the matter at hand, since a variety of methods can be done with the apparatus. The method limitations are viewed as intended uses which do not further limit, and therefore do not patentably distinguish the claimed invention. The apparatus of Leeser et al. is capable of performing the claimed limitations if the method to be performed within the apparatus requires it.
Regarding claim 7, it should be noted that the impedance matcher comprises a capacitor module including a plurality of variable capacitors CT and CS that would be connected to the plurality of substate supports and the variable capacitors have capacitance changed in accordance with the impedance compensation values (see, for example, Fig. 3B and 4B-D and their descriptions, Fig. 3B is shown above).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leeser et al., US 2020/0244244 in view of Nguyen et al., US 2018/0047544, as applied to claims 1-2 and 7 above, and further in view of Tomita et al., US 2011/0234100 or Hoffman et al., US 2007/0080138.
Leeser et al. and Nguyen et al. are applied as above and Leeser et al. further discloses that the sensor module is within the substrate support but does not expressly disclose that the sensor module is connected to a lower surface of the substrate support. Tomita et al. discloses an apparatus for processing substrates having a sensor 100b connected to the lower surface of a substrate support 217 to detect the voltages flowing through the lower surface of the substrate support (see, for example, Fig. 1 and its description, Fig. 1 is shown below).
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Additionally, Hoffman et al. discloses an apparatus for processing substrates having a sensor 132 connected to the lower surface of a substrate support 115 to detect the voltages and current flowing through the lower surface of the substrate support (see, for example, Fig. 1 and its description, Fig. 1 is shown below).
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Therefore, in view of this disclosure, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Leeser et al. modified by Nguyen et al., as to connect the sensor module to a lower surface of the substrate support because such configuration is known and used in the art as a suitable configuration to effectively, efficiently, and accurately detect the voltages and the currents flowing through the lower surface of the substrate support.
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive.
Applicant argues that Leeser et al. and Nguyen et al. fail to teach or suggest “wherein the impedance matcher selects one of the plurality of stages as a master stage, and the impedance matchers sets an impedance of the master stage as the reference impedance; wherein the master stage has a maximum radio frequency (RF current value among RF current values of the plurality of stages that are measured while transmitting RF power that generates the plasma through a ground path of the plurality of stages while the substrates are simultaneously processed”.
With respect to Leeser et al., applicant argues that the reference teaches adjusting the maximum value to meet the minimum value, not to match an impedance of a master stage having a maximum radio frequency (RF) current, and therefore, Leeser et al. fails to teach or suggest that “the impedance matcher sets an impedance of the master stage as the reference impedance; wherein the master stage has a maximum radio frequency (RF) current value among RF current values of the plurality of stages” as required by independent claim 1. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). It should be noted that the secondary reference of Nguyen et al. has been relied upon for its teachings of an apparatus for processing substrates having a plurality of processing spaces and plurality of impedance circuits that are configured in a master-slave relationship. With respect to the master stage having a maximum RF current value among RF current values of the plurality of stages that are measured, it should be noted that such limitation is directed to a method limitation instead of an apparatus limitation, and since an apparatus is being claimed as the instant invention, the method teachings are not considered to be the matter at hand, since a variety of methods can be done with the apparatus. The method limitations are viewed as intended uses which do not further limit, and therefore do not patentably distinguish the claimed invention. The impedance matcher of the apparatus of Leeser et al. modified by Nguyen et al. is capable of performing the claimed master-slave relationship wherein the master stage has a maximum RF current value if the method to be performed within the apparatus requires it. Additionally, it should be noted that the specification of the instant claimed invention clearly discloses that the master stage can be selected from the stage having the maximum current value, the stage having an average (nearest average) value, or can be the stage having the minimum value (see, for example, paragraphs 0050-0051 of the specification of the instant claimed invention). Therefore, there is no evidence that the choice of a particular value for the master stage would significantly affect the overall performance of the plasma processing apparatus. Furthermore, and this notwithstanding a prima facie case of obviousness still exists because it would have been obvious to one of ordinary skill in the art before the invention was filed to use a substrate support having a desired current value as the master substrate support, depending upon, for example, the desired plasma uniformity, characteristics, and/or density, and such limitation would not lend patentability to the instant application absent the showing of unexpected results.
Regarding Nguyen et al., applicant argues that Nguyen et al. teaches comparing impedances between the showerhead and the liner to tune and control plasma, not to find a maximum RF current value among different stages to identify a master stage, and use an impedance of the master stage as the reference impedance. The examiner respectfully disagrees and contends that Nguyen et al. in, for example, paragraph 0019, clearly discloses independently tuning the impedances using the first and second impedance circuits, wherein the first and second impedance circuits are coupled to a controller that controls the impedances to achieve a desired plasma shape by configuring the first and second impedance circuits in a master-slave relationship.
Applicant further argues that Nguyen et al. fails to teach or suggest that “the impedance matcher sets an impedance of the master stage as the reference impedance; wherein the master stage has a maximum radio frequency (RF) current value among RF current values of the plurality of stages” as required by independent claim 1. As stated above, with respect to the master stage having a maximum RF current value among RF current values of the plurality of stages that are measured, the examiner respectfully points out that such limitation is directed to a method limitation instead of an apparatus limitation, and since an apparatus is being claimed as the instant invention, the method teachings are not considered to be the matter at hand, since a variety of methods can be done with the apparatus. The method limitations are viewed as intended uses which do not further limit, and therefore do not patentably distinguish the claimed invention. The impedance matcher of the apparatus of Leeser et al. modified by Nguyen et al. is capable of performing the claimed master-slave relationship wherein the master stage has a maximum RF current value if the method to be performed within the apparatus requires it. Additionally, it should be noted that the specification of the instant claimed invention clearly discloses that the master stage can be selected from the stage having the maximum current value, the stage having an average (nearest average) value, or can be the stage having the minimum value (see, for example, paragraphs 0050-0051 of the specification of the instant claimed invention). Therefore, there is no evidence that the choice of a particular value for the master stage would significantly affect the overall performance of the plasma processing apparatus. Furthermore, and this notwithstanding a prima facie case of obviousness still exists because it would have been obvious to one of ordinary skill in the art before the invention was filed to use a substrate support having a desired current value as the master substrate support, depending upon, for example, the desired plasma uniformity, characteristics, and/or density, and such limitation would not lend patentability to the instant application absent the showing of unexpected results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsujimoto et al. (US 2021/0305030) is cited for its teaching of an apparatus for processing substrates comprising an impedance matching circuit.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUZ L ALEJANDRO whose telephone number is (571)272-1430. The examiner can normally be reached Monday and Thursday, 8:30 a.m. - 5:00 p.m..
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/LUZ L ALEJANDRO MULERO/Primary Examiner, Art Unit 1716
May 25, 2026
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