Prosecution Insights
Last updated: April 19, 2026
Application No. 18/462,386

METHOD FOR PROCESSING SUBSTRATE

Non-Final OA §103
Filed
Sep 06, 2023
Examiner
REMAVEGE, CHRISTOPHER
Art Unit
1713
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Psk Inc.
OA Round
1 (Non-Final)
57%
Grant Probability
Moderate
1-2
OA Rounds
3y 4m
To Grant
84%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allow Rate
361 granted / 632 resolved
-7.9% vs TC avg
Strong +27% interview lift
Without
With
+26.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
29 currently pending
Career history
661
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
26.1%
-13.9% vs TC avg
§112
15.5%
-24.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 632 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (KR 100976604 B1) in view of Buzaglo et al. (US 20210334946 A1). As to claim 1, Lee discloses a substrate treating method [Abstract; claim 1] comprising: treating an edge region of a substrate using a plasma [Background; pg. 7, para. 7]; and acquiring an image to be determined by imaging a substrate on which a treatment has been completed in the treating the edge region [pg. 7, para. 6], comparing the image to be determined with an image stored in a database [pg. 7, para. 7, “pre-stored good wafer”], and determining whether a substrate treated in the treating the edge region is defective or not [pg. 7, para. 7]. Lee discloses comparing the acquired image of the wafer with the image of a pre-stored good wafer, in order to determine if the wafer to be inspected is defective [pg. 7, para. 7], and therefore fails to explicitly disclose: wherein the image stored in the database is a defective image of a substrate which has been determined as defective, which is previously stored in the database in the acquiring the image to be determined. However, Buzaglo et al. (US 20210334946 A1) teaches a method for classifying and inspecting for defects in semiconductor wafers [Abstract; claim 1] comprising: wherein the image stored in the database is a defective image of a substrate which has been determined as defective, which is previously stored in the database in the acquiring the image to be determined [claim 1; para. 0037-38]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of comparing the acquired image of the semiconductor wafer with a reference image of a good wafer to determine if the wafer to be inspected is defective, of Lee, to include applying different deep learning models, including comparing the acquired image of a semiconductor with reference images of both good wafers and wafers containing various defects, of Buzaglo, in order to improve detection of defective wafers, as taught by Buzaglo [para. 0037-38]. As to claim 2, modified Lee discloses the substrate treating method of claim 1, wherein in the acquiring the image to be determined, if the image to be determined matches any one among defective images [Buzaglo, claim 1], it is determined that a treatment is defective in the treating the edge region [Lee, pg. 7, para. 7]. As to claim 3, modified Lee discloses the substrate treating method of claim 2, wherein if the image to be determined matches any one among the defective images, the image to be determined is stored in the database [Buzaglo, para. 0037-38, “dynamically classify”]. As to claim 4, modified Lee discloses the substrate treating method of claim 1, wherein if the image to be determined matches any one among the defective images, a maintenance operation with respect to a component of a process chamber performing the treating the edge region is performed [Lee, pg. 7, para. 7]. As to claim 8, modified Lee discloses the substrate treating method of claim 1, wherein at the acquiring the image to be determined, whether a boundary displayed on the image to be determined and a boundary displayed on the defective image is determined, and the boundary is between the edge region of the substrate which is treated by the plasma and a central region of the substrate [Lee, pg. 7, para. 7]. Claims 5, 9-12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (KR 100976604 B1) in view of Buzaglo et al. (US 20210334946 A1), as applied to claims 1-4 and 8 above, and further in view of Chan et al. (KR 102305139 B1). As to claim 5, modified Lee discloses the substrate treating method of claim 4, but fails to explicitly disclose the plasma apparatus a recited in claim 5. However, Chan et al. (KR 102305139 B1) teaches a load lock chamber and apparatus for treating a substrate edge region with a plasma process [Abstract; claims 1 and 6; pg. 10, para. 2], comprising: wherein the process chamber includes: a support unit 300 configured to support the substrate W [pg. 8-9; Fig. 3]; a dielectric plate 520 positioned above the support unit to face a central region of a substrate supported on the support unit [pg. 8-9; Fig. 3]; and a plasma source generating a plasma at an edge region of the substrate supported on the support unit [pg. 8-9; Fig. 3], and wherein the component includes a dielectric plate [pg. 8-9; Fig. 3]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plasma etching apparatus for removing a film at a bevel region of a wafer and having upper and lower electrodes, of Lee, to include the plasma etching apparatus including upper and lower electrodes, a support unit, and a dielectric plate facing the support unit and load lock chamber for imaging, of Chan, in order to more efficiently remove a film at an edge/bevel region of a wafer, as taught by Chan [pg. 10, para. 2]. As to claim 9, modified Lee discloses the substrate treating method of claim 1 wherein the substrate having the edge region treated is transferred to a load lock chamber in the treating the edge region, and the acquiring the image to be determined is performed in the load lock chamber [Chan, claims 1 and 6]. As to claim 10, modified Lee discloses the substrate treating method of claim 9, wherein in the load lock chamber the image to be determined is acquired by imaging the edge region of the chamber by rotating the substrate [Chan, claims 1 and 6]. As to claim 11, modified Lee discloses a substrate treating method [Abstract] comprising: treating an edge region of a substrate using a plasma at a process chamber including a plasma source generating the plasma at the edge region [pg. 7, para. 7]; acquiring an image to be determined by imaging a substrate on which a treatment is completed [pg. 7, para. 6], and determining whether the image to be determined and an image stored in a database match [pg. 7, para. 7; Buzaglo, claim 1]; and performing a maintenance operation on the dielectric plate if the image to be determined matches at least any one among images stored in the database [pg. 7, para. 7; Buzaglo, claim 1]. Modified Lee fails to explicitly disclose: the substrate supported on a support unit and a dielectric plate positioned above the support unit to face the support unit. However, Chan et al. (KR 102305139 B1) teaches a load lock chamber and apparatus for treating a substrate edge region with a plasma process [Abstract; pg. 10, para. 2], comprising: the substrate W supported on a support unit 300 and a dielectric plate 520 positioned above the support unit to face the support unit [pg. 8-9; Fig. 3]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plasma etching apparatus for removing a film at a bevel region of a wafer and having upper and lower electrodes, of Lee, to include the plasma etching apparatus including upper and lower electrodes, a support unit, and a dielectric plate facing the support unit, of Chan, in order to more efficiently remove a film at an edge/bevel region of a wafer, as taught by Chan [pg. 10, para. 2]. As to claim 12, modified Lee discloses the substrate treating method of claim 11, wherein the image stored in the database is a defective image of a substrate which has been determined as needing the maintenance operation, which is previously stored in the database [Lee, pg. 7, para. 7; Buzaglo, claim 1]. As to claim 16 modified Lee discloses the substrate treating method of claim 12, wherein whether the image to be determined matches the defective image is determined based on whether a boundary displaying the image to be determined and a boundary displayed on the defective image match, and the boundary is between the edge region of the substrate which is treated by the plasma the central region of the substrate [Lee, pg. 7, para. 7]. Allowable Subject Matter Claims 6-7 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: As to claims 6, the prior art of record fails to teach, alone or in combination, the feature of “wherein when the image to be determined matches any one among the defective images, when the image to be determined is stored in the database, a data of a current state of the dielectric plate matching the image to be determined is stored in the database, and if it is determined that a subsequent image to be determined matches at least any one among the defective images, a replacement time of the dielectric plate is determined based on the data which is matched with the subsequent image to be determined.” Claim 7 is considered to contain allowable subject matter based on its dependence on claim 6. As to claim 13, the prior art of record fails to teach, alone or in combination, the feature of “wherein when the image to be determined matches any one among defective images and the image to be determined is stored in the database, a data of a current state of the dielectric plate matching the image to be determined is stored in the database, and if it is determined that a subsequent image to be determined matches at least any one among the defective images, a replacement time of the dielectric plate is determined based on the data which is matched with the subsequent image to be determined.” Claims 14 and 15 are considered to contain allowable subject matter based on their dependence on claim 13. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: The additionally cited references are cited to show methods of imaging and processing images of semiconductor wafers [Abstracts]. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER M REMAVEGE whose telephone number is (571)-270-5511. The examiner can normally be reached Monday-Friday 10:00 AM - 3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER REMAVEGE/Examiner, Art Unit 1713
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Prosecution Timeline

Sep 06, 2023
Application Filed
Feb 21, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
57%
Grant Probability
84%
With Interview (+26.7%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 632 resolved cases by this examiner. Grant probability derived from career allow rate.

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