DETAILED ACTION
This action is responsive to the communication filed 7 July 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species I embodiment in the reply filed on 16 December 2025 is acknowledged.
Accordingly, claims 7, 11, and 20 are withdrawn from further consideration.
Drawings
The objections to the drawings are withdrawn, responsive to Applicant’s arguments and amendments.
Claim Rejections - 35 USC § 112
Applicant’s amendment of claim 14 has clarified the scope of claim 14 with respect to one portion of the claim language noted in the Non-Final Rejection mailed 9 March 2026, but ambiguity still exists regarding the other portion of the claim language noted in the Non-Final Rejection. Accordingly, the rejection is maintained with respect to that portion of the claim language.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.’” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313 (Fed. Cir. 2014)).
Regarding Claim 14: Claim 14 states, in relevant part, “wherein the buffer layer includes inorganic material, the first insulating layer includes inorganic material, and/or the second insulating layer includes inorganic material.” It is unclear whether Applicant’s use of the phrase “and/or” encompasses (1) a configuration wherein all, one, or two of the recited layers may be the inorganic layer, or (2) a configuration wherein either only the buffer layer and first insulating layer includes organic material, but not the second insulating layer, or vice versa. For the purposes of examination, the abovementioned terminology has been interpreted in accordance with interpretation (1).
Claims 15 and 16, which depend from claim 14, are also rejected under § 112(b) for the same reasons as claim 14.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-6, 8-10, and 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2023/0134901 (filed Oct. 19, 2022) (hereinafter “Ko”) in view of U.S. Patent Publication No. 2023/0178655 (effectively filed Aug. 30, 2022) (hereinafter “Tanaka”).
Regarding independent claim 1, Ko discloses: A display panel, comprising:
a light emitting element (FIG. 16, display element 710, [0229]); and
a pixel circuit (FIG. 16, depicting a plurality of transistors including first and second thin film transistors TR1 and TR2, [0231]) electrically connected to the light emitting element, the pixel circuit including a first transistor (FIG. 16, second thin film transistor TR2) and a second transistor (FIG. 16, first thin film transistor TR1),
wherein the first transistor (FIG. 16, second thin film transistor TR2) includes:
a first semiconductor pattern (FIG. 16, active layer A2, [0247]) including a first source region (FIG. 16, source electrode S2, [0247]), a first drain region (FIG. 16, drain electrode D2, [0247]), and a first channel region that is disposed between the first source region and the first drain region (FIG. 16, depicting the channel portion of the active layer A2 between the drain electrode D2 and the source electrode S2);
a first gate electrode disposed over the first channel region (FIG. 16, depicting the gate electrode G2 disposed over the channel portion, [0247]); and
a first conductive pattern disposed under the first channel region (FIG. 16, depicting the light-shielding layer 111 disposed under the channel portion),
wherein the second transistor includes (FIG. 16, first thin film transistor TR1):
a second semiconductor pattern (FIG. 16, active layer A1, [0247]) including a second source region (FIG. 16, source electrode S1, [0246]), a second drain region (FIG. 16, drain electrode D1, [0246]), and a second channel region that is disposed between the second source region and the second drain region (FIG. 16, depicting the channel portion of the active layer A1 between the drain electrode D1 and the source electrode S1);
a second gate electrode disposed over the second channel region (FIG. 16, depicting the gate electrode G1 disposed over the channel portion, [0246]); and
a second conductive pattern disposed under the second channel region (FIG. 16, depicting the light-shielding layer 111 disposed under the channel portion),
wherein the first conductive pattern overlaps the first gate electrode (FIG. 16, depicting wherein the light shielding layer 111 overlaps the gate electrode G2),
wherein a length of the first conductive pattern is longer than a length of the first gate electrode, in a cross-sectional view taken along a direction from the source region to the drain region of the first semiconductor pattern (FIG. 16, depicting wherein the length of the light shielding layer 111 is longer than the length of the gate electrode G2 along a direction from the source electrode S2 to the drain electrode D2),
wherein the second conductive pattern overlaps the second gate electrode (FIG. 16, depicting wherein the light shielding layer 111 overlaps the gate electrode G1).
Ko discloses in [0262] wherein the light shielding layer 111 may be connected to the gate electrode G1. Ko does not specifically disclose wherein a length of the second conductive pattern is shorter than a length of the second gate electrode, in a cross-sectional view taken along a direction from the source region to the drain region of the second semiconductor pattern.
In the same field of endeavor, Tanaka discloses a display panel (FIG. 1, display device 1, [0042]) including a transistor (FIG. 17, depicting a dual-gate TFT, [0032]), wherein the transistor has a configuration such that a length of a second conductive pattern (FIG. 17, bottom gate electrode 710, [0136]) is shorter than a length of a second gate electrode (FIG. 17, top gate electrode 750, [0136]) in a cross-sectional view taken along a direction from the source region to the drain region of the second semiconductor pattern (FIG. 17, depicting wherein the top gate electrode 750 is longer than the bottom gate electrode 710 in a direction from one S/D electrode region 770 to another S/D electrode region 770, [0137]). Regarding the configuration of the electrodes of the transistor, in [0142], Tanaka states: “This configuration in FIG. 17 also provides the same effect as the configuration in FIG. 16 , which prevents the vicinities of the ends defining the channel length from reducing in resistance, and further, an effect of attaining high on-state current because both the top-gate electrode region 750 and the bottom-gate electrode region 710 apply gate fields.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device of Ko by substituting the transistor configuration of Tanaka, such that the light shielding layer 111 may have a length that is shorter than the length of the gate electrode G1 along a direction from the source electrode S1 to the drain electrode D1, in order to reduction in resistance of ends of the channel and improve on-state current. See Tanaka [0142].
Regarding claim 3, Ko in view of Tanaka further discloses the first semiconductor pattern and the second semiconductor pattern are disposed on a same layer (FIG. 16, depicting wherein the active layers A1/A2 are disposed on a same layer).
Regarding claim 4, Ko in view of Tanaka further discloses wherein the first conductive pattern and the second conductive pattern include a same material (FIG. 16, [0074]: “The light shielding layer 111 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), or iron (Fe).”).
Regarding claim 5, Ko in view of Tanaka further discloses wherein the first conductive pattern and the second conductive pattern are disposed on a same layer (FIG. 16, depicting wherein the light shielding layers 111 are disposed on a same layer).
Regarding claim 6, Ko in view of Tanaka further discloses wherein the length of the second conductive pattern is shorter than the length of the first conductive pattern (FIG. 16, depicting wherein the length of the light shielding layer 111 overlapping the active layer A1 is shorter than the length of the light shielding layer 111 overlapping the active layer A2).
Regarding claim 8, Ko in view of Tanaka further discloses wherein the second channel region has a stepped shape corresponding to an outer end of the second conductive pattern (Ko FIG. 16; Tanaka FIG. 17; depicting wherein the channel region of the active layer A1, as modified by Tanaka, would have a stepped shape corresponding to the outer end of the light shielding layer 111).
Regarding claim 9, Ko in view of Tanaka further discloses wherein the second gate electrode has a stepped shape corresponding to the stepped shape of the second channel region (Ko FIG. 16; Tanaka FIG. 17; depicting wherein the gate electrode G1, as modified by Tanaka, would have a stepped shape corresponding to the outer end of the light shielding layer 111 and the channel region of the active layer A1).
Regarding claim 10, Ko in view of Tanaka further discloses wherein the second conductive pattern is electrically connected to the second gate electrode (FIG. 16, depicting wherein the light shielding layer 111 is electrically connected to the gate electrode G1, [0262]).
Regarding claim 12, Ko in view of Tanaka further discloses wherein the light emitting element includes a first electrode (FIG. 16, first electrode 711, [0266]), a second electrode (FIG. 16, second electrode 713, [0266]), and an emissive layer that is disposed between the first electrode and the second electrode (FIG. 16, depicting an organic light emitting layer 712 disposed between the first and second electrodes 711/713), and wherein the first electrode is electrically connected to the first source region (FIG. 16, depicting wherein the first electrode 711 is electrically connected to the source electrode S2).
Regarding claim 13, Ko in view of Tanaka further discloses wherein the first source region is electrically connected to the first gate electrode (FIG. 16, depicting wherein the source electrode S2 is electrically connected to the gate electrode S2).
Regarding claim 14, Ko in view of Tanaka further discloses a buffer layer disposed between the first conductive pattern and the first channel region (FIG. 16, depicting, e.g., buffer layer 121, disposed between the light shielding layer 111 and the channel portion of the active layer A2, [0076]); a first insulating layer disposed between the first channel region and the first gate electrode (FIG. 16, depicting, e.g., gate insulating layer 141, disposed between the channel portion of the active layer A2 and the gate electrode G2, [0151]); and a second insulating layer disposed on the first gate electrode (FIG. 16, depicting, e.g., gate insulating layer 142, disposed on the gate electrode G2, [0151]), wherein the buffer layer includes inorganic material ([0076]: “The first buffer layer 121 may include at least one of a silicon oxide, a silicon nitride or a metal-based oxide.”), the first insulating layer includes inorganic material ([0094]: “The gate insulating layer 140 may include at least one of a silicon oxide, a silicon nitride or a metal-based oxide. The gate insulating layer 140 may have a single layered structure, or may have a multi-layered structure.”), and/or the second insulating layer includes inorganic material ([0094]: “The gate insulating layer 140 may include at least one of a silicon oxide, a silicon nitride or a metal-based oxide. The gate insulating layer 140 may have a single layered structure, or may have a multi-layered structure.”).
Regarding claim 15, Ko in view of Tanaka further discloses wherein the buffer layer is thicker than the first insulating layer (FIG. 16, depicting wherein the buffer layer 121 is thicker than the gate insulating layer 141)
Regarding claim 16, Ko in view of Tanaka further discloses wherein the first insulating layer (FIG. 16, gate insulating layer 141) includes an insulating pattern that overlaps the first channel region (FIG. 16, gate insulating layer 141) without overlapping the first source region or the first drain region (FIG. 16, depicting wherein the gate insulating layer 141 does not overlap that portion of the source electrode S2 directly under the bridge BR1).
Regarding independent claim 17, Ko discloses:
a light emitting element (FIG. 16, display element 710, [0229]); and
a pixel circuit (FIG. 16, depicting a plurality of transistors including first and second thin film transistors TR1 and TR2, [0231]) electrically connected to the light emitting element, the pixel circuit including a drive transistor (FIG. 16, second thin film transistor TR2, which is a driving transistor, [0231]) and a switching transistor (FIG. 16, first thin film transistor TR1, which is a switching transistor, [0231]),
wherein the drive transistor (FIG. 16, second thin film transistor TR2) includes:
a first semiconductor pattern (FIG. 16, active layer A2, [0247]) including a first channel region (FIG. 16, depicting the channel portion of the active layer A2 between the drain electrode D2 and the source electrode S2), a first source region (FIG. 16, source electrode S2, [0247]), and a first drain region (FIG. 16, drain electrode D2, [0247]);
a first gate electrode disposed over the first channel region (FIG. 16, depicting the gate electrode G2 disposed over the channel portion, [0247]) and electrically connected to the first source region (FIG. 16, depicting wherein the gate electrode G2 is electrically connected to the source electrode S2); and
a first conductive pattern disposed under the first channel region (FIG. 16, depicting the light-shielding layer 111 disposed under the channel portion),
wherein the switching transistor (FIG. 16, first thin film transistor TR1) includes:
a second semiconductor pattern (FIG. 16, active layer A1, [0247]) including a second channel region (FIG. 16, depicting the channel portion of the active layer A1 between the drain electrode D1 and the source electrode S1), a second source region (FIG. 16, source electrode S1, [0246]), and a second drain region (FIG. 16, drain electrode D1, [0246]);
a second gate electrode disposed over the second channel region (FIG. 16, depicting the gate electrode G1 disposed over the channel portion, [0246]); and
a second conductive pattern disposed under the second channel region (FIG. 16, depicting the light-shielding layer 111 disposed under the channel portion),
wherein the second conductive pattern overlaps the second gate electrode (FIG. 16, depicting wherein the light shielding layer 111 overlaps the gate electrode G1).
Ko discloses in [0262] wherein the light shielding layer 111 may be connected to the gate electrode G1. Ko does not specifically disclose wherein a length of the second conductive pattern is shorter than a length of the second gate electrode, in a cross-sectional view taken along a direction from the source region to the drain region of the second semiconductor pattern.
In the same field of endeavor, Tanaka discloses a display panel (FIG. 1, display device 1, [0042]) including a transistor (FIG. 17, depicting a dual-gate TFT, [0032]), wherein the transistor has a configuration such that a length of a second conductive pattern (FIG. 17, bottom gate electrode 710, [0136]) is shorter than a length of a second gate electrode (FIG. 17, top gate electrode 750, [0136]) in a cross-sectional view taken along a direction from the source region to the drain region of the second semiconductor pattern (FIG. 17, depicting wherein the top gate electrode 750 is longer than the bottom gate electrode 710 in a direction from one S/D electrode region 770 to another S/D electrode region 770, [0137]). Regarding the configuration of the electrodes of the transistor, in [0142], Tanaka states: “This configuration in FIG. 17 also provides the same effect as the configuration in FIG. 16 , which prevents the vicinities of the ends defining the channel length from reducing in resistance, and further, an effect of attaining high on-state current because both the top-gate electrode region 750 and the bottom-gate electrode region 710 apply gate fields.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device of Ko by substituting the transistor configuration of Tanaka, such that the light shielding layer 111 may have a length that is shorter than the length of the gate electrode G1 along a direction from the source electrode S1 to the drain electrode D1, in order to reduction in resistance of ends of the channel and improve on-state current. See Tanaka [0142].
Regarding claim 18, Ko in view of Tanaka further discloses wherein in a plan view, an outer end of the first conductive pattern is spaced apart from the first channel region (FIG. 16, depicting wherein, in a plan view, an outer end of the light shielding layer 111 is spaced apart from the channel portion of the active layer A2), and an outer end of the second conductive pattern overlaps the second channel region (FIG. 16, depicting wherein an outer end of the light shielding layer 111 of Ko, as modified by Tanaka, would overlap the channel portion of the active layer A1).
Regarding claim 19, Ko in view of Tanaka further discloses wherein each of the second channel region (Ko FIG. 16; Tanaka FIG. 17; depicting wherein the channel region of the active layer A1, as modified by Tanaka, would have a stepped shape) and the second gate electrode has a stepped shape (Ko FIG. 16; Tanaka FIG. 17; depicting wherein the gate electrode G1, as modified by Tanaka, would have a stepped shape).
Claim 2 is rejected under 35 U.S.C. § 103 as being unpatentable over Ko in view of Tanaka, and further in view of U.S. Patent Publication No. 2022/0208793 (filed Dec. 22, 2021) (hereinafter “Takahata”).
Regarding claim 2, Ko in view of Tanaka further discloses wherein each of the first semiconductor pattern and the second semiconductor pattern includes an oxide semiconductor material (FIG. 16, [0245]: “Each of the first active layer A1 and the second active layer A2 may include, for example, an oxide semiconductor material.”). Ko in view of Tanaka does not specifically disclose wherein the first semiconductor pattern and the second semiconductor pattern include a metal oxide semiconductor material.
In the same field of endeavor, in [0237], Takahata a semiconductor layer comprising a metal oxide semiconductor material.
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known semiconductor material, such as one including an oxide semiconductor, as shown by Takahata in [0237], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose an oxide semiconductor material over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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