DETAILED ACTION
This action is responsive to U.S. Patent Application No. 18/462,389 filed on 6 September 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species I embodiment in the reply filed on 16 December 2025 is acknowledged.
Accordingly, claims 7, 11, and 20 are withdrawn from further consideration.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed feature of claim 18 wherein “wherein in a plan view, an outer end of the first conductive pattern is spaced apart from the first channel region, and an outer end of the second conductive pattern overlaps the second channel region.” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.’” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313 (Fed. Cir. 2014)).
Regarding Claim 14: Claim 14 states, in relevant part, “wherein the buffer layer, the first insulating layer, and/or the second insulating layer includes an inorganic layer.” The relevant phrasing renders the scope of the claim unclear for several reasons. First, it is unclear whether the recited limitation encompasses (1) a configuration wherein the “inorganic layer” is one or more of the buffer layer, first insulating layer, or second insulating layer, or (2) a configuration wherein there are one or more “inorganic layers” additional to the buffer layer, first insulating layer, and second insulating layer. For the purposes of examination, the abovementioned phrasing has been interpreted in accordance with interpretation (1).
Second, it is unclear whether the phrase “and/or” encompasses (1) a configuration wherein all, one, or two of the recited layers may be the inorganic layer, or (2) a configuration wherein only all or only one of the buffer layer, first insulating layer, or second insulating layer may be the inorganic layer. For the purposes of examination, the abovementioned terminology has been interpreted in accordance with interpretation (1).
Claims 15 and 16, which depend from claim 14, are also rejected under § 112(b) for the same reasons as claim 14.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-10, and 14-19 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by U.S. Patent Publication No. 2022/0208793 (filed Dec. 22, 2021) (hereinafter “Takahata”).
Regarding independent claim 1, Takahata discloses: A display panel (FIG. 1, active matrix substrate 1000 including a display area DR, [0058]), comprising:
a light emitting element (FIG. 1, pixel areas PIX corresponding to the pixels of a display device, [0058]); and
a pixel circuit (FIG. 1, [0061]: “Each of the pixel areas PIX has a pixel transistor (pixel TFT) Tp and a pixel electrode PE.”) electrically connected to the light emitting element (FIG. 1, [0061]: “The pixel transistor Tp has a gate electrode electrically connected to a corresponding one of the gate bus lines GL, a source electrode electrically connected to a corresponding one of the source bus lines SL, and a drain electrode electrically connected to the pixel electrode PE.”),
the pixel circuit including a first transistor (FIGS. 1/2, depicting a second TFT 200, [0073]) and a second transistor (FIGS. 1/2, depicting a first TFT 100, [0073]),
wherein the first transistor includes:
a first semiconductor pattern (FIGS. 1/2, oxide semiconductor layer 6, [0075]) including a first source region (FIGS. 1/2, e.g., source contact region 64s, [0093]),
a first drain region (FIGS. 1/2, e.g., drain contact region 64d, [0093]), and
a first channel region (FIGS. 1/2, e.g., second channel region 61, [0093]) that is disposed between the first source region and the first drain region (FIGS. 1/2, depicting wherein the second channel region 61 is disposed between the source and drain contact regions 64s/64d);
a first gate electrode (FIGS. 1/2, gate electrode 7B, [0088]) disposed over the first channel region (FIGS. 1/2, depicting wherein the gate electrode 7B is disposed over the second channel region 61); and
a first conductive pattern (FIGS. 1/2, lower conductive layer 2B, [0098]) disposed under the first channel region (FIGS. 1/2, depicting wherein the lower conductive layer 2B is disposed under the second channel region 61),
wherein the second transistor includes:
a second semiconductor pattern (FIGS. 1/2, oxide semiconductor layer 4, [0076]) including a second source region (FIGS. 1/2, e.g., source contact region 44s, [0080]),
a second drain region (FIGS. 1/2, e.g., source contact region 44d, [0080]), and
a second channel region (FIGS. 1/2, e.g., first channel region 41 and offset regions 42, [0078]) that is disposed between the second source region and the second drain region (FIGS. 1/2, depicting wherein the first channel region 41 and offset regions 42 are disposed between the source and drain contact regions 44s/44d);
a second gate electrode (FIGS. 1/2, gate electrode 7A, [0076]) disposed over the second channel region (FIGS. 1/2, depicting wherein the gate electrode 7A is disposed over the first channel region 41 and offset regions 42); and
a second conductive pattern (FIGS. 1/2, lower conductive layer 2A, [0086]) disposed under the second channel region (FIGS. 1/2, depicting wherein the lower conductive layer 2A is disposed under the first channel region 41 and offset regions 42),
wherein the first conductive pattern overlaps the first gate electrode (FIGS. 1/2, depicting wherein the lower conductive layer 2B overlaps the gate electrode 7B),
wherein a length of the first conductive pattern is longer than a length of the first gate electrode (FIGS. 1/2, depicting in, e.g., FIG. 2A wherein a length of the lower conductive layer 2B is longer than a length of the gate electrode 7B),
wherein the second conductive pattern overlaps the second gate electrode (FIGS. 1/2, depicting wherein the lower conductive layer 2A overlaps the gate electrode 7A), and
wherein a length of the second conductive pattern is shorter than a length of the second gate electrode (FIGS. 1/2, depicting in, e.g., FIG. 2A wherein a length of the lower conductive layer 2A is shorter than a length of the gate electrode 7A).
Regarding claim 2, Takahata further discloses wherein each of the first semiconductor pattern (FIGS. 1/2, oxide semiconductor layer 6, [0075]) and the second semiconductor pattern (FIGS. 1/2, oxide semiconductor layer 4, [0076]) includes a metal oxide semiconductor material (FIGS. 1/2, [0237]: “The oxide semiconductor (also referred to as “metal oxide” or “oxide material”) contained in the oxide semiconductor layer of each TFT in the present embodiment may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion.”).
Regarding claim 3, Takahata further discloses wherein the first semiconductor pattern (FIGS. 1/2, oxide semiconductor layer 6, [0075]) and the second semiconductor pattern (FIGS. 1/2, oxide semiconductor layer 4, [0076]) are disposed on a same layer (FIGS. 1/2, depicting wherein each of the oxide semiconductor layers 4/6 are disposed on a same first insulating film 51, [0081]).
Regarding claim 4, Takahata further discloses wherein the first conductive pattern (FIGS. 1/2, lower conductive layer 2B, [0098]) and the second conductive pattern (FIGS. 1/2, lower conductive layer 2A, [0086]) include a same material (FIGS. 1/2, [0126]: “Next, the lower conducting film is patterned by a publicly-known photolithography step. In this way, as shown in FIG. 4A, the lower conductive layer 2A is formed in the first TFT formation region r1, and the lower conductive layer 2B is formed in the second TFT formation region r2.”; [0128]: “The lower conducting film is not particular material but can be made of a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), an alloy thereof, or a film containing a metal nitride thereof as appropriate.”).
Regarding claim 5, Takahata further discloses wherein the first conductive pattern (FIGS. 1/2, lower conductive layer 2B, [0098]) and the second conductive pattern (FIGS. 1/2, lower conductive layer 2A, [0086]) are disposed on a same layer (FIGS. 1/2, depicting wherein each of the lower conductive layers 2A/2B are disposed on, e.g., a same substrate 1, [0078])
Regarding claim 8, Takahata further discloses wherein the second channel region has a stepped shape (FIGS. 1/2, depicting wherein the first channel region 41 and offset regions 42 form a 90 degree edge, i.e. a step) corresponding to an outer end of the second conductive pattern (FIGS. 1/2, depicting wherein the outer end of the lower conductive layer 2A also includes a step shape similar to that formed by the outer ends of the first channel region 41 and offset regions 42).
Regarding claim 9, Takahata further discloses wherein the second gate electrode (FIGS. 1/2, gate electrode 7A) has a stepped shape corresponding to the stepped shape of the second channel region (FIGS. 1/2, depicting wherein the outer end of the gate electrode 7A also includes a step shape similar to that formed by the outer ends of the first channel region 41 and offset regions 42).
Regarding claim 10, Takahata further discloses wherein the second conductive pattern (FIGS. 1/2, lower conductive layer 2A, [0086]) is electrically connected to the second gate electrode (FIGS. 1/2, [0102]: “[T]he lower conductive layers 2A . . . may function as lower gate electrodes by being electrically connected to the gate electrodes 7A”).
Regarding claim 14, Takahata further discloses a buffer layer (FIGS. 1/2, insulating layer 3, [0086]) disposed between the first conductive pattern and the first channel region (FIGS. 1/2, depicting wherein the insulating layer 3 is disposed between the lower conductive layer 2B and the second channel region 61);
a first insulating layer (FIGS. 1/2, insulating film 52, [0081]) disposed between the first channel region and the first gate electrode (FIGS. 1/2, depicting wherein the insulating film 52 is disposed between the second channel region 61 and the gate electrode 7B); and
a second insulating layer (FIGS. 1/2, insulating layer 10, [0084]) disposed on the first gate electrode (FIGS. 1/2, depicting wherein the insulating layer 10 is disposed on the gate electrode 7B), wherein the buffer layer, the first insulating layer, and/or the second insulating layer includes an inorganic layer (FIGS. 1/2, [0167]: “As the interlayer insulating layer 10, a single inorganic insulating layer or a stack of inorganic insulating layers can be formed.”).
Regarding claim 15, Takahata further discloses wherein wherein the buffer layer is thicker than the first insulating layer (FIGS. 1/2, depicting wherein the insulating layer 3 is thicker than the insulating film 52).
Regarding claim 16, Takahata further discloses wherein the first insulating layer (FIGS. 1/2, insulating film 52) includes an insulating pattern that overlaps the first channel region without overlapping the first source region or the first drain region (FIGS. 1/2, depicting wherein the insulating film 52 overlaps the second channel region 61 but not the source or drain regions 64s/64d).
Regarding independent claim 17, Takahata discloses: A display panel (FIG. 1, active matrix substrate 1000 including a display area DR, [0058]), comprising:
a light emitting element (FIG. 1, pixel areas PIX corresponding to the pixels of a display device, [0058]); and
a pixel circuit (FIG. 1, [0061]: “Each of the pixel areas PIX has a pixel transistor (pixel TFT) Tp and a pixel electrode PE.”) electrically connected to the light emitting element (FIG. 1, [0061]: “The pixel transistor Tp has a gate electrode electrically connected to a corresponding one of the gate bus lines GL, a source electrode electrically connected to a corresponding one of the source bus lines SL, and a drain electrode electrically connected to the pixel electrode PE.”),
the pixel circuit including a drive transistor (FIGS. 1-10, depicting a second TFT 200, [0073]; [0110]: “[A] drive circuit may include a mixture of first TFTs 100 and second TFTs 200.”; [0225]: “Alternatively, a second TFT having great current drive force (high mobility) is used as at least the TFT 34, which is an output transistor, and first TFTs may be used as the other TFTs. This allows the drive circuit to have a mixture of two types of TFT of different characteristics depending on its intended use.”) and a switching transistor (FIGS. 1/2, depicting a first TFT 100, [0073]; [0110]: “[A] drive circuit may include a mixture of first TFTs 100 and second TFTs 200.”; [0225]: “Alternatively, a second TFT having great current drive force (high mobility) is used as at least the TFT 34, which is an output transistor, and first TFTs may be used as the other TFTs. This allows the drive circuit to have a mixture of two types of TFT of different characteristics depending on its intended use.”),
wherein the drive transistor includes:
a first semiconductor pattern (FIGS. 1/2, oxide semiconductor layer 6, [0075]) including a first channel region (FIGS. 1/2, e.g., second channel region 61, [0093]),
a first source region (FIGS. 1/2, e.g., source contact region 64s, [0093]), and
a first drain region (FIGS. 1/2, e.g., drain contact region 64d, [0093]);
a first gate electrode (FIGS. 1/2, gate electrode 7B, [0088]) disposed over the first channel region (FIGS. 1/2, depicting wherein the gate electrode 7B is disposed over the second channel region 61) and electrically connected to the first source region (FIGS. 1/2, depicting wherein the gate electrode 7B is electrically connected to the source contact region 64s); and
a first conductive pattern (FIGS. 1/2, lower conductive layer 2B, [0098]) disposed under the first channel region (FIGS. 1/2, depicting wherein the lower conductive layer 2B is disposed under the second channel region 61),
wherein the switching transistor includes:
a second semiconductor pattern (FIGS. 1/2, oxide semiconductor layer 4, [0076]) including a second channel region (FIGS. 1/2, e.g., first channel region 41 and offset regions 42, [0078]),
a second source region (FIGS. 1/2, e.g., source contact region 44s, [0080]), and
a second drain region (FIGS. 1/2, e.g., source contact region 44d, [0080]);
a second gate electrode (FIGS. 1/2, gate electrode 7A, [0076]) disposed over the second channel region (FIGS. 1/2, depicting wherein the gate electrode 7A is disposed over the first channel region 41 and offset regions 42); and
a second conductive pattern (FIGS. 1/2, lower conductive layer 2A, [0086]) disposed under the second channel region (FIGS. 1/2, depicting wherein the lower conductive layer 2A is disposed under the first channel region 41 and offset regions 42),
wherein the second conductive pattern overlaps the second gate electrode (FIGS. 1/2, depicting wherein the lower conductive layer 2A overlaps the gate electrode 7A), and
wherein a length of the second conductive pattern is shorter than a length of the second gate electrode (FIGS. 1/2, depicting in, e.g., FIG. 2A wherein a length of the lower conductive layer 2A is shorter than a length of the gate electrode 7A).
Regarding claim 18, Takahata further discloses wherein in a plan view, an outer end of the first conductive pattern (FIGS. 1/2, lower conductive layer 2B) is spaced apart from the first channel region (FIGS. 1/2, depicting wherein in a plan view, e.g., the top left corner of the lower conductive layer 2B is spaced apart from the second channel region 61), and an outer end of the second conductive pattern (FIGS. 1/2, lower conductive layer 2A) overlaps the second channel region (FIGS. 1/2, depicting wherein in a plan view, e.g., at least a part of the left side of the lower conductive layer 2A overlaps the first channel region 41 and offset regions 42).
Regarding claim 19, Takahata further discloses wherein each of the second channel region (FIGS. 1/2, first channel region 41 and offset regions 42) and the second gate electrode (FIGS. 1/2, gate electrode 7A) has a stepped shape (FIGS. 1/2, depicting wherein the outer ends of the first channel region 41 and offset regions 42 and the gate electrode 7A form an angle creating a step shape).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. § 103 as being unpatentable over Takahata.
Regarding claim 6, while Takahata states in [0104] that “the planar shapes, sizes, channel lengths, channel widths, or other attributes of the layers of the first and second TFTs 100 and 200 need only be set depending on the uses of the TFTs, and may be different from each other,” Takahata does not specifically disclose wherein the length of the second conductive pattern is shorter than the length of the first conductive pattern.
Regarding the relative lengths of the lower conductive layers 2A/2B, however, it is well-established that “when there is motivation to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP § 2143(I)(E) (quoting KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, (2007)).
Currently, there is a recognized need in the art to create display devices that maximize performance and minimize cost, often accomplished by using fewer and/or smaller amounts of materials in each layer comprising the device such that the layers are short enough to improve the shorten processing windows with minimal steps, but long enough to meet desired performance specifications. In the present case, there are a finite number of identified, predictable potential solutions for meeting the abovementioned need in the context of material usage, including forming the lower conductive layer 2A to be shorter than the lower conductive layer 2B, forming the lower conductive layer 2A to be equal in length to the lower conductive layer 2B, or forming the lower conductive layer 2A to be longer than the lower conductive layer 2B, each having a reasonable expectation of success regardless of which known potential solution is pursued.
Accordingly, it would have been obvious to try forming the lower conductive layer 2A to be shorter than the lower conductive layer 2B.
Claims 12 and 13 are rejected under 35 U.S.C. § 103 as being unpatentable over Takahata in view of U.S. Patent Publication No. 2021/0408177 (filed July 12, 2019) (hereinafter “Fan”).
Regarding claim 12, Takahata does not specifically disclose wherein the light emitting element includes a first electrode, a second electrode, and an emissive layer that is disposed between the first electrode and the second electrode, and wherein the first electrode is electrically connected to the first source region.
In the same field of endeavor, Fan discloses a display device including a light emitting element (FIG. 2, display back panel 250, [0031]) including a first electrode (FIG. 2, first electrode 300, [0031]), a second electrode (FIG. 2, second electrode 600, [0031]), and an emissive layer (FIG. 2, light emitting layer 500, [0031]) that is disposed between the first electrode and the second electrode (FIG. 2, depicting wherein the light emitting layer 500 is disposed between the first electrode 300 and the second electrode 600). Regarding the light emitting element configuration, in [0002], Fan states: “An organic light-emitting diode (OLED) display device is a self-luminous display device that emits light through an OLED to display an image, and is thinner, lighter, and has improved display characteristics (e.g., a higher contrast ratio) relative to a display device including a liquid crystal display (LCD).”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device of Takahata by adding the light emitting element configuration of Fan in order to improve thinness, lightness, and display characteristics of the display device. See Fan [0002].
Moreover, the addition of the light emitting element configuration of Fan would result in a configuration wherein the first electrode (Fan FIG. 2, first electrode 300) is electrically connected to the first source region (Takahata FIGS. 1/2, e.g., depicting wherein the first electrode 300 would be electrically connected to the source contact region 64s, just as the pixel electrode PE of Takahata is electrically connected to the source contact region 64s).
Regarding claim 13, Takahata in view of Fan further discloses wherein the first source region (FIGS. 1/2, e.g., source contact region 64s) is electrically connected to the first gate electrode (FIGS. 1/2, depicting wherein the source contact region 64s is electrically connected to the gate electrode 7B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos: 2019/0051672 (filed Nov. 9, 2016); 2023/0075289 (filed Aug. 25, 2022); 2023/0207570 (effectively filed July 3, 2020); 2017/0110049 (published Apr. 20, 2017); 2023/0276665 (effectively filed Feb. 28, 2022).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813